®
ISO
2
-CMOS ST-BUS™ FAMILY
MT9092
Digital Telephone with HDLC (HPhone-II)
Features
•
•
•
•
Programmable µ-Law/A-Law codec and filters
Programmable CCITT (G.711)/sign-magnitude
coding
Programmable transmit, receive and side-tone
gains
DSP-based:
i) Speakerphone switching algorithm
ii) DTMF and single tone generator
iii) Tone Ringer
Differential interface to telephony transducers
Differential audio paths
Single 5 volt power supply
X.25 Level 2 HDLC data formatting
ISSUE 2
May 1995
Ordering Information
MT9092AP
44 Pin PLCC
-40°C to +85°C
Description
The MT9092 HPhone-II is a fully featured integrated
digital telephone circuit which includes an HDLC
data formatter. Voice band signals are converted to
digital PCM and vice versa by a switched capacitor
Filter/Codec. The Filter/Codec uses an ingenious
differential architecture to achieve low noise
operation over a wide dynamic range with a single
5V supply. A Digital Signal Processor provides
handsfree speaker-phone operation. The DSP is
also used to generate tones (DTMF, Ringer and Call
Progress) and control audio gains. Internal registers
are accessed through a serial microport conforming
to INTEL MCS-51™ specifications. The device is
fabricated in Mitel's low power ISO
2
-CMOS
technology.
•
•
•
•
Applications
•
•
•
Fully featured digital telephone sets
Cellular phone sets
Local area communications stations
DSTo
DSTi
F0i
C4i
VSSD
VDD
VSSA
VSS
SPKR
VBias
VRef
Digital Signal Processor
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22.5/-72dB
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∆1.5dB
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Rx
AAAAAA
Tx &
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Filter/Codec Gain
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7dB
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ENCODER
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AAAA
DECODER
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-7dB
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MIC-
Transducer
Interface
MIC+
M-
M+
C-Channel
Registers
STATUS
Control
Registers
HSPKR+
HSPKR-
SPKR+
HDLC
SPKR-
Timing
Circuits
New Call
Tone
Generator
Serial
Port
(
MCS-51
Compatible)
LCD Driver
S/P &
P/S
Converter
DATA 2
DATA 1
SCLK
CS
IRQ
S1
S12
BP
WD PWRST IC
Figure 1 - Functional Block Diagram
7-3
MT9092
PWRST
IC
VRef
VBias
NC
M+
M-
VSSA
MIC+
MIC-
VSS SPKR
DSTi
DSTo
C4i
F0i
VSSD
IRQ
SCLK
DATA 2
DATA 1
CS
WD
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
SPKR+
SPKR-
HSPKR+
HSPKR-
VDD
BP
S12
S11
S10
S9
S8
Pin Description
Pin
#
1
2
3
4
5
6
7
8
Name
M+
NC
V
Bias
V
Ref
IC
Description
Non-Inverting Microphone (Input).
Non-inverting input to microphone amplifier from the
handset microphone.
No Connect.
No internal connection to this pin.
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external amplifiers.
Connect 0.1 µF capacitor to V
SSA
.
Reference voltage for codec (Output).
Nominally [(V
DD
/2)-1.5] volts. Used internally.
Connect 0.1 µF capacitor to V
SSA
.
Internal Connection.
Tie externally to V
SS
for normal operation.
PWRST
Power-up Reset (Input).
CMOS compatible input with Schmitt Trigger (active low).
DSTi
DSTo
ST-BUS Serial Stream (Input).
2048 kbit/s input stream composed of 32 eight bit channels;
the first four of which are used by the MT9092. Input level is TTL compatible.
ST-BUS Serial Stream (Output).
2048 kbit/s output stream composed of 32 eight bit
channels. The MT9092 sources digital signals during the appropriate channel, time coincident
with the channels used for DSTi.
4096 kHz Clock (Input).
CMOS level compatible.
Frame Pulse (Input).
CMOS level compatible. This input is the frame synchronization pulse
for the 2048 kbit/s ST-BUS stream.
Digital Ground .
Nominally 0 volts.
Interrupt Request (Open Drain Output).
An active low output indicating an unmasked HDLC
interrupt event. Requires 1 kΩ pull-up to V
DD
.
Serial Port Synchronous Clock (Input).
Data clock for MCS-51 compatible microport. TTL
level compatible.
9
10
11
12
13
C4i
F0i
V
SSD
IRQ
SCLK
7-4
IC
NC
NC
VSSD
S1
S2
S3
S4
S5
S6
S7
44 PIN PLCC
18
19
20
21
22
23
24
25
26
27
28
Figure 2 - Pin Connections
MT9092
Pin Description (continued)
Pin
#
14
Name
Description
DATA 2
Serial Data Transmit.
In an alternate mode of operation, this pin is used for data transmit
from MT9092. In the default mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is tri-stated.
DATA 1
Bidirectional Serial Data.
Port for microprocessor serial data transfer compatible with MCS-
51 standard (default mode). In an alternate mode of operation , this pin becomes the data
receive pin only and data transmit is performed on the DATA 2 pin. Input level TTL compatible.
CS
WD
IC
NC
V
SSD
Chip Select (Input).
This input signal is used to select the device for microport data
transfers. Active low. (TTL level compatible.)
Watchdog (Output).
Watchdog timer output. Active high.
Internal Connection.
Tie externally to V
SS
for normal operation.
No Connection.
No internal connection to these pins.
Digital Ground.
Nominally 0 volts.
15
16
17
18
19,
20
21
22-
33
34
35
36
37
38
39
40
41
42
43
44
S1-S12
Segment Drivers (Output).
12 independently controlled, two level, LCD segment drivers. An
in-phase signal, with respect to the BP pin, produces a non-energized LCD segment. An out-
of-phase signal, with respect to the BP pin, energizes its respective LCD segment.
BP
V
DD
Backplane Drive (Output).
A two-level output voltage for biasing an LCD backplane.
Positive Power Supply (Input).
Nominally 5 volts.
HSPKR-
Inverting Handset Speaker (Output).
Output to the handset speaker (balanced).
HSPKR
Non-Inverting Handset Speaker (Output).
Output to the handset speaker (balanced).
+
SPKR-
Inverting Speaker (Output).
Output to the speakerphone speaker (balanced).
SPKR+
Non-Inverting Speaker (Output).
Output to the speakerphone speaker (balanced).
V
SS
SPKR
MIC-
MIC+
V
SSA
M-
Power Supply Rail for Analog Output Drivers.
Nominally 0 Volts.
Inverting Handsfree Microphone (Input).
pin.
Handsfree microphone amplifier inverting input
Handsfree microphone amplifier non-
Non-inverting Handsfree Microphone (Input).
inverting input pin.
Analog Ground.
Nominally 0 V.
Inverting Microphone (Input).
Inverting input to microphone amplifier from the handset
microphone.
NOTES:
Intel and MCS-51 are registered trademarks of Intel Corporation, Santa Clara, CA, USA.
7-5
MT9092
Overview
The functional block diagram of Figure 1 depicts the
main operations performed within the HPhone-II.
Each of these functional blocks will be described in
the sections to follow. This overview will describe
some of the end-user features which may be
implemented as a direct result of the level of
integration found within the HPhone-II.
The main feature required of a digital telephone is to
convert the digital Pulse Code Modulated (PCM)
information, being received by the telephone set, into
an analog electrical signal. This signal is then
applied to an appropriate audio transducer such that
the information is finally converted into intelligible
acoustic energy. The same is true of the reverse
direction where acoustic energy is converted first
into an electrical analog and then digitized (into
PCM) before being transmitted from the set. Along
the way if the signals can be manipulated, either in
the analog or the digital domains, other features
such as gain control, signal generation and filtering
may be added. More complex processing of the
digital signal is also possible and is limited only be
the processing power available. One example of this
processing power may be the inclusion of a complex
handsfree switching algorithm. Finally, most electro-
acoustic transducers (loudspeakers) require a large
amount of power to develop an effective acoustic
signal. The inclusion of audio amplifiers to provide
this power is required.
The HPhone-II features Digital Signal Processing
(DSP) of the voice encoded PCM, complete Analog/
Digital and Digital/Analog conversion of audio
signals (Filter/CODEC) and an analog interface to
the external world of electro-acoustic devices
(Transducer Interface). These three functional blocks
combine to provide a standard full-duplex telephone
conversation utilizing a common handset. Selecting
transducers for handsfree operation, as well as
allowing the DSP to perform its handsfree switching
algorithm, is all that is required to convert the full-
duplex handset conversation into a half-duplex
speakerphone conversation. In each of these
modes, full programmability of the receive path and
side-tone gains is available to set comfortable
listening levels for the user as well as transmit path
gain control for setting nominal transmit levels into
the network.
The HPhone-II’s HDLC block is easy to use in
proprietary signalling protocols such as those within
PABXs and Key Systems. A fully interrupt driven
interface, buffered by 19 byte FIFOs in each
direction,
simplifies
the
microcontroller's
asynchronous access to the D-Channel information.
7-6
The ability to generate tones locally provides the
designer with a familiar method of feedback to the
telephone user as they proceed to set-up, and
ultimately, dismantle a telephone conversation. Also,
as the network slowly evolves from the dial pulse/
DTMF methods to the D-Channel protocols it is
essential that the older methods be available for
backward compatibility. As an example; once a call
has been established, say from your office to your
home, using the D-Channel signalling protocol it may
be necessary to use in-band DTMF signalling to
manipulate your personal answering machine in
order to retrieve messages. Thus the locally
generated tones must be of network quality and not
just a reasonable facsimile. The HPhone-II DSP can
generate the required tone pairs as well as single
tones to accommodate any in-band signalling
requirement.
Each of the programmable parameters within the
functional blocks is accessed through a serial
microcontroller port compatible with Intel MCS-51
specifications.
Functional Description
In this section, each functional block within the
HPhone-II is described along with all of the
associated control/status bits. Each time a control/
status bit(s) is described it is followed by the address
register where it will be found. The reader is referred
to the section titled ‘Register Summary' for a
complete listing of all address map registers, the
control/status bits associated with each register and
a definition of the function of each control/status bit.
The Register Summary is useful for future reference
of control/status bits without the need to locate them
within the text of the functional descriptions.
Filter-CODEC
The Filter/CODEC block implements conversion of
the analog 3.3kHz speech signals to/from the digital
domain compatible with 64kb/s PCM B-Channels.
Selection of companding curves and digital code
assignment are register programmable. These are
CCITT G.711 A-law or µ-Law, with true-sign/
Alternate Digit Inversion or true-sign/Inverted
Magnitude coding, respectively. Optionally, sign-
magnitude coding may also be selected for
proprietary applications.
The Filter/CODEC block also implements transmit
and receive audio path gains in the analog domain.
These gains are in addition to the digital gain pad
provided in the DSP section and provide an overall
path gain resolution of 0.5dB. A programmable gain,
MT9092
voice side-tone path is also included to provide
proportional transmit speech feedback to the
handset receiver so that a dead sounding handset is
not encountered. Figure 3 depicts the nominal half-
channel and side-tone gains for the HPhone-II.
On PWRST (pin 6) the Filter/CODEC defaults such
that the side-tone path, dial tone filter and 400Hz
transmit filter are off, all programmable gains are set
to 0dB and µ-Law companding is selected. Further,
the Filter/CODEC is powered down due to the PuFC
bit (Transducer Control Register, address 0Eh) being
reset. This bit must be set high to enable the Filter/
CODEC.
The internal architecture is fully differential to provide
the best possible noise rejection as well as to allow a
wide dynamic range from a single 5 volt supply
design. This fully differential architecture is
continued into the Transducer Interface section to
provide full chip realization of these capabilites.
A reference voltage (V
Ref
), for the conversion
requirements of the CODER section, and a bias
voltage (V
Bias
), for biasing the internal analog
sections, are both generated on-chip. V
Bias
is also
brought to an external pin so that it may be used for
biasing any external gain plan setting amplifiers. A
0.1µF capacitor must be connected from V
Bias
to
analog ground at all times. Likewise, although V
Ref
may only be used internally, a 0.1µF capacitor from
the V
Ref
pin to ground is required at all times. It is
suggested that the analog ground reference point for
these two capacitors be physically the same point.
SERIAL
PORT
DSP GAIN*
FILTER/CODEC
TRANSDUCER INTERFACE
µ-Law
–6.3 dB
Α-Law
–3.7 dB
-6 dB
HSPKR+
75
Handset
Receiver
(150Ω)
Receive
PCM
–72 to
+22.5 dB
(1.5dB
steps)
Receive
Filter Gain
0 to –7 dB
(1 dB steps)
-6 dB
Receiver
Driver
HSPKR–
75
Side-tone
–9.96 to
+9.96dB
(3.32 dB steps)
DTMF,
Tone
Ringer &
Handsfree
Speaker
Phone
Driver
0.2dB*
SPKR+
SPKR–
Speaker Gain
0 to –24 dB
(8 dB steps)
Tone
Ringer
(input
from DSP)
Speakerphone
Speaker
(40Ω nominal)
(32Ω min)
Side-tone
Nominal
Gain
µ-Law
–11 dB
Α-Law
–18.8 dB
PCM
–72 to
+22.5 dB
(1.5dB
steps)
Transmit
DIGITAL DOMAIN
Transmit
Filter Gain
0 to +7dB
(1 dB steps)
µ-Law
6.1dB
Α-Law
15.4dB
Transmit
Gain
M
U
X
MIC+ Handsfree
MIC– mic
M+
M–
Transmitter
microphone
ANALOG DOMAIN
Internal to Device
Note: *gain the same for A-Law and
µ−
Law
External to Device
Figure 3 - Audio Gain Partitioning
7-7
FPGA/CPLD
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