CMOS
®
MT90733
DS3 Framer (DS3F)
Advance Information
Features
•
•
•
•
•
•
•
•
•
DS3 payload access in either bit-serial or
nibble-parallel mode
C-bit parity or M13 operating mode
Separate interface for C-bits
Detect and generate DS3 AIS, and idle signals
Transmit reference generator for serial
operation
Transmit and receive FEAC channel under
software control
Transmit single errors: framing, FEBE, C-bit
parity, and P-bit parity
FEBE, C-bit and P-bit performance counters
Transmit-to-Receive and Receive-to-Transmit
loopbacks
Subrate multiplexing
Wideband data or video transport
DS3 monitor and test
Channel extenders
Line Side
X1
X2
FE
D3RD
D3RC
CRD
CRCK
CRF
CRDCC
STUFC
STUFD
AD(7-0)
WR
RD
ALE
SEL
OENA
FORCEOE
CXD
CXCK
CXF
CXDCC
D3TD
D3TC
FORCECP
FORCEPP
FORCFEBE
U.S. Patent Number 5040170
ISSUE 1
May 1995
Ordering Information
MT90733AP
68 Pin PLCC
-40° to 85°C
Description
The MT90733 DS3 Framer (DS3F) is designed for
mapping broadband payloads into the DS3 frame for-
mat, which meets ANSI’s T1.107-1988 and supple-
ment T1.107a-1990.
Although the C-bit parity format is recommended, the
DS3F can also operate in the M13 mode. In the C-bit
parity format, the DS3F provides a separate interface
for selected C-bits. The DS3F also provides software
access for transmitting and receiving the FEAC chan-
nel, and generates and detects DS3 AIS, DS3 idle, P-
bit parity and C-bit parity. In addition, performance
counters are provided, as well as the ability to gener-
ate single framing, FEBE, C-bit parity and P-bit parity
errors. The payload interface is selectable through
software as either a bit-serial or nibble-parallel format.
Terminal Side
Applications
•
•
•
•
Receive
Serial Parallel
DS3
Receive
DS3
Interpreter
Output
N.C.
N.C.
N.C.
RDS
RCS
RCG
RFS
RNIB3
RNIB2
RNIB1
RNIB0
RCN
N.C.
RFN
µP
I/O
Transmit
Frame
Reference
Generator
TDOUT
TCG
TFOUT
TCOUT
TFIN
TCIN
N.C.
N.C.
XCK
XFSI
XDS
N.C.
N.C.
N.C.
XFNO
XCN
XCK
N.C.
XNIB3
XNIB2
XNIB1
XNIB0
Input
DS3
Send
Transmit
Figure 1 - Functional Block Diagram
5-23
MT90733
CMOS
Advance Information
CXDCC
OENA
XFNO
CXCK
D3RC
D3TD
D3TC
TEST
VDD
XNC
VDD
XCK
62
CXF
VSS
VSS
SEL
FORCfEBE
61
10
68
67
66
65
64
ALE
X1
RD
X2
WR
STUFD
STUFC
VDD
AD7
AD6
AD5
AD4
VSS
AD3
AD2
AD1
AD0
27
63
9
8
7
6
5
4
3
2
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
XNIB0
XNIB1
XNIB2
FORCECP
XDS/XNIB3
FORCEPP
FORCEOE
VSS
TCIN
VDD
XFSI
TFIN
TCOUT
TFOUT
TCG
TDOUT
VSS
44
RFS/RFN
RCS/RCN
CXD
VDD
CRD
D3RD
CRDCC
RCG
VDD
CRF
VSS
CRCK
Figure 2 - Pin Connections
Pin Description
Power Supply & Ground
Pin #
4, 17, 27
38, 51, 63
6, 22, 33
44, 53, 67
Name
VDD
VSS
I/O/P
P
P
Power Supply Input.
+5v± 5%.
Ground.
Description
Note: I = Input; O = Output; P = Power
DS3 Receive Line Side Interface
Pin #
5
29
Name
D3RC
D3RD
I/O/P
I
I
Description
DS3 Receive Clock.
A 44.736 MHz clock used for clocking in receive data,
and as the time base for the DS3F receiver.
DS3 Receive Data.
DS3 line side serial receive data.
Note: I = Input; O = Output; P = Power
5-24
RDS/RNIB0
RNIB3
RNIB2
RNIB1
FE
Advance Information
CMOS
MT90733
DS3 Transmit Line Side Interfac
e
Pin #
1
3
Name
D3TC
D3TD
I/O/P
O
O
Description
DS3 Transmit Clock.
A 44.736 MHz clock that is derived from the transmit
clock (XCK) signal and is used for clocking out the line side DS3 data signal.
DS3 Transmit Data.
DS3 line side serial transmit data.
Note: I = Input; O = Output; P = Power
Receive Terminal Side Interfac
e
Pin #
31
32
34
39
40
41
42
Name
RFS
/
RFN
I/O/P
O
O
O
O
Description
Receive Framing Pulse for Serial/Nibble Interface.
The framing pulse is
synchronous with the first bit 1 in the DS3 frame or nibble 1175.
Receive Clock Gap Signal.
The active low gap signal is synchronous with
each overhead bit in the serial DS3 frame (first bit in the 85-bit group).
Receive Clock for Serial/Nibble Interface.
Clock used for clocking out the
terminal side receive serial and nibble data.
Receive Nibble/Serial Interface.
Nibble data is clocked out on positive transi-
tions of the nibble clock (RCN). Serial data is clocked out on negative transi-
tions of the receive clock (RCS).
RCG
RCS/RCN
RNIB3
RNIB2
RNIB1
RDS/RNIB0
Note: I = Input; O = Output; P = Power
Transmit Terminal Side Interfac
e
Pin #
2
50
56
58
59
60
62
Name
XFNO
I/O/P
O
I
I
Description
Transmit Framing Pulse for Nibble Interface.
An active low, one nibble clock
cycle wide (XCN) pulse that occurs during the second nibble time.
Transmit Framing Pulse for Serial Interface:
A framing pulse input that must
be synchronous with bit 1 in the transmit serial data DS3 frame.
Transmit Nibble/Serial Interface.
Nibble data is clocked in on positive transi-
tions of the nibble clock (XCN). Serial data is clocked into the DS3F on posi-
tive transitions of the transmit clock (XCK).
Transmit Clock.
A 44.736 Mbit/s clock input with a stability of
±20
ppm and a
duty cycle of 50
±10%.
XCK provides the time base for the transmitter in the
DS3F.
Transmit Clock for Nibble Interface.
Output clock signal derived from the
transmit clock (XCK).
XFSI
XDS/XNIB3
XNIB2
XNIB1
XNIB0
XCK
I
66
XCN
O
Note: I = Input; O = Output; P = Power
5-25
MT90733
CMOS
Advance Information
Transmit Reference Generator Interfac
e
Pin #
45
Name
TDOUT
I/O/P
O
Description
Transmit Reference Generator Data Output.
A DS3 frame is provided on
this signal lead with only the appropriate M and F bits. All other bits in the
frame are held active low.
Transmit Reference Generator Clock Gap Signal.
An active low, one clock
cycle wide (TCOUT) output signal that is synchronous with bit 1 in each 85-bit
group (56 overhead bits) in the DS3 frame.
Transmit Reference Generator Framing Pulse.
An active low, one clock
cycle wide (TCOUT) output pulse that is synchronous with bit 1 in the DS3
frame.
Transmit Reference Generator Clock Out.
Clock signal that is derived from
the transmit reference generator clock input (TCIN).
Transmit Reference Generator Clock In.
A 44.736 Mbit/s clock with a stabil-
ity of
±20
ppm and a duty cycle of 50
±10%.
46
TCG
O
47
TFOUT
O
48
52
TCOUT
TCIN
O
I
Note: I = Input; O = Output; P = Power
Receive C-Bit Interface
Pin #
30
Name
CRDCC
I/O/P
O
Description
C-Bit Receive Data Link Clock.
A gapped clock provided for clocking in the
three data link bits (C13, C14, and C15) into external circuitry from the serial
data (CRD).
C-Bit Receive Framing Pulse.
Provides a time base reference for clocking in
the C-bits in a DS3 frame.
C-Bit Receive Clock.
A gapped clock which clocks C-bit data out of the DS3F
on positive transitions.
C-Bit Receive Data.
Serial interface for receiving the selected C-bits in the C-
bit parity mode.
35
36
37
CRF
CRCK
CRD
O
O
O
Note: I = Input; O = Output; P = Power
Transmit C-Bit Interface
Pin #
28
64
65
68
Name
CXD
CXDCC
CXF
CXCK
I/O/P
I
O
O
O
Description
C-Bit Transmit Data.
Serial interface for transmitting the selected C-bits in the
C-bit parity mode.
C-Bit Transmit Data Link Clock.
A gapped clock provided for clocking the
three data link bits (C13, C14, and C15).
C-Bit Transmit Framing Pulse.
Identifies the location of the first C-bit in the
DS3 frame.
C-Bit Transmit Clock.
A gapped clock which clocks the external C-bit serial
data into the DS3F on positive transitions.
Note: I = Input; O = Output; P = Power
5-26
Advance Information
Other Signals
Pin #
7
9
Name
TEST
OENA
I/O/P
I
O
Test Pin:
Leave open.
Description
CMOS
MT90733
Overhead Enable.
An active high signal that enables an overhead error to be
introduced into the overhead bit in the next 85th group by placing a low on the
FORCEOE lead.
DS3 Received X-Bit 1.
An output indication of the state of the first X-bit
received in the DS3 frame.
DS3 Received X-Bit 2.
An output indication of the state of the second X-bit
received in the DS3 frame (bit 680).
Stuff Data Status.
This output signal provides an indication of the state of the
stuff opportunity bit from the received DS3F frame.
Stuff Clock.
Provided for clocking out the stuff opportunity bit state.
Framing Error Indication.
An active high signal is generated when a framing
error is detected while in frame alignment. The framing error indication is held
active low when a DS3 out of frame alarm occurs.
Optional Framing Input Pulse.
Not required for normal operation.
Force DS3 Overhead Bit Error.
An active low input signal used in conjunction
with the overhead enable signal (OENA) for introducing an overhead bit error
in the next transmitted 85-bit group.
Force P-Bit Parity Error.
An active low input signal generates and transmits a
P-bit error by inverting both P-bits.
Force C-Bit Parity Error.
An active low input signal generates and transmits a
C-bit parity error when operating in the C-bit parity mode.
Force FEBE Error.
An active low input signal generates and transmits a far
end block error (FEBE) when operating in the C-bit parity mode.
11
13
15
16
43
X1
X2
STUFD
STUFC
FE
O
O
O
O
O
49
54
TFIN
FORCEOE
I
I
55
57
61
FORCEPP
FORCECP
FORCFEBE
I
I
I
Note: I = Input; O = Output; P = Power
Microprocesssor Interface
Pin #
8
10
12
14
18-21
23-26
Name
SEL
ALE
RD
WR
AD(7-4)
AD(3-0))
I/O/P
I
I
I
I
I/O
Description
Microprocessor Select.
A low enables the processor to access the DS3F
memory map for control, status and alarm information.
Address Latch Enable.
An active high input signal is used by the processor
to hold an address stable during a read/write bus cycle on the falling edge.
Read.
An active low input signal generated by the processor for reading the
registers which reside in the DS3F memory map.
Write.
An active low input signal generated by the processor for writing to the
registers which reside in the memory map.
Address/Data Bus.
These leads constitute the time multiplexed address and
data bus for accessing the registers which reside in the DS3F memory map.
Note: I = Input; O = Output; P = Power
5-27
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