®
MT90732
CMOS
E2/E3 Framer (E2/E3F)
Advance Information
Features
•
Framer for CCITT Recommendations
- G.742 (8448 kbit/s)
- G.745 (8448 kbit/s)
- G.751 (34368 kbit/s)
- G.753 (34368 kbit/s)
Line side interface
- Dual rail or NRZ
HDB3 codec for dual rail I/O
Terminal side interface
- Nibble-parallel
- Bit-serial
Transmit reference generator for bit-serial I/O
Microprocessor or control leads
I/O port for service bits
ISSUE 1
May 1995
Ordering Information
MT90732AP
68 Pin PLCC
-40°C to +85°C
Description
The MT90732 E2/E3 Framer (E2/E3F) is a CMOS
VLSI device that provides the functions needed to
frame a wideband payload to one of four CCITT
Recommendations. G.742, G.745, G.751, or G.753.
The E2/E3 Framer interfaces to line circuitry with
either dual rail or NRZ signals. On the terminal side,
the interface can be either nibble-parallel or bit-
serial.
The MT90732 can be operated with or without a
microprocessor.
When
interfaced
with
a
microprocessor, the E2/E3 Framer provides an 8-
byte memory map for control, performance counters
and alarm status. The MT90732 provides a transmit
and receive interface port for accessing the
overhead
bits
from
each
of
the
four
recommendations. The overhead bits can also be
accessed by the microprocessor via the memory
map.
SERIAL
PARALLEL
RNIB3
RNIB2
RNIB1
RNIB0
RNC
RNF
N.C.
•
•
•
•
•
•
Applications
•
•
•
•
Line terminals
Wideband data or video transport
Test equipment
Multiplexer systems
RDL
RCKL
RP/RDL
RN
RCK/RCKL
CV
RAIS
RLOC
BIP-4E
RLOF
ROD
ROC
ROF
FE
NRZ LINE
BIP-4
M0
M1
MICRO
SER
DAIS
TLBK
PLBK
TAIS
LPT
TLCINV
TLOC
FORCEFE
TOD
TOC
TOF
RESET
TP/TDL
TCK/TCKL
Line Side
TN
Data
Line
Decoder
Clock
Framer
Data
Clock
Frame
Interpreter
Data
Clock
Frame
Output
RSD
TDOUT
TCG
TFOUT
RSC
RSF
RCG
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
SEL
ALE
RD
WR
RDY
Micro-
processor
I/O
Control
Transmit
Reference
Generator
XSF
N.C.
TCIN
XSD
XCK
N.C.
TCOUT
XNIB3
XNIB2
XNIB1
XNIB0
XCK
XNF
XNC
TCKL
TDL
Line
Encoder
Data
Clock
G.7XX
Send
Clock
Data
Framing
Input
Terminal Side
U.S. Patent Number 5040170
Figure 1 - Functional Block Diagram
5-15
MT90732
CMOS
RNIB2/TDOUT
RNIB0/TFOUT
RNIB3/RSD
RNIB1/TCG
RCK/RCKL
Advance Information
RNC/RSC
RNF/RSF
62
RP/RDL
RLOC
RLOF
RAIS
GND
ROD
VDD
RN
CV
RCG
61
10
68
67
66
65
64
ROC
ROF
FE
NRZLINE
BIP-4
M0
M1
VDD
GND
MICRO
SER
TLBK
PLBK
TAIS
LPT
TLOC
FORCEFE
27
63
9
8
7
6
5
4
3
2
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
BIP-4E
XNC/TCOUT
XNF
XCK
XNIB0/XSD
XNIB1/TCIN
XNIB2
XNIB3/XSF
GND
VDD
TLCINV
DAIS
RDY
WR
RD
ALE
SEL
44
TCK/TCKL
TP/TDL
AD7
AD6
AD5
AD4
AD3
AD2
AD1
TOD
TOC
GND
RESET
Figure 2 - Pin Connections
Pin Description
Power Supply and Ground
Pin #
1,17,35,51
18,34,52,68
Name
VDD
GND
I/O/P
P
P
Description
VDD.
5-volt supply voltage, +/- 5%
Ground.
Note: I = Input; O = Output; P = Power
Line Side Receive
Pin #
2
3
4
Name
RP/RDL
RN
RCK/RCKL
I/O/P
I
I
I
Description
Receive Positive Rail/Receive NRZ Data.
Receive positive rail/NRZ data
generated from line interface circuit.
Receive Negative Rail Data.
Receive negative rail data generated from line
interface circuit.
Receive Clock Rail/Receive Clock NRZ.
The receive clock is used for clock-
ing in the rail/NRZ data signals.
Note: I = Input; O = Output; P = Power
5-16
VDD
TOF
AD0
TN
Advance Information
CMOS
MT90732
Line Side Transmit
Pin #
31
32
Name
TP/TDL
TCK/TCKL
I/O/P
O
O
Description
Transmit Positive Rail/Transmit NRZ Data.
Transmit positive rail/NRZ data
sent out of E2/E3 Framer.
Transmit Clock Rail/Transmit Clock NRZ.
The transmit clock is used for
clocking out the dual rail/NRZ data signals. The TCK/TCKL clock signal is
derived from the XCK clock.
Transmit Negative Rail Data.
Transmit negative rail data sent out of E2/E3
Framer.
33
TN
O
Note: I = Input; O = Output; P = Power
Terminal Interface
Pin #
61
62
Name
RCG
RNF/RSF
I/O/P
O
O
Description
Receive Clock Gapped.
An active low signal indicates the receive framing
and service bit locations in the serial mode only.
Receive Framing Pulse.
Framing pulse is synchronous with the last nibble for
the nibble-parallel interface, and with the first bit in the frame for the bit-serial
interface.
Receive Nibble Bit 3/Receive Serial Data.
Bit 3 is the most significant bit in
the nibble and corresponds to the first bit received in the nibble. The framing
pattern, service bits, and BIP-4 nibble are not provided as parallel data. In the
serial mode receive data signal consists of all bits, including the framing pat-
tern and service bits.
Receive Nibble Bit 2/Transmit Reference Generator Data Output.
In the
nibble-parallel mode, it is Bit 2 of the received nibble.The reference generator
is enabled in the serial mode. The output data signal (TDOUT) consists of all
ones in place of the framing bits and zeros elsewhere in the frame.
Receive Nibble Bit 1/Transmit Reference Generator Clock Gap Signal.
In
the nibble-parallel mode, it is Bit 1 of the received nibble. The active low TCG
signal indicates the location of the framing pattern and the service bits in the
frame.
Receive Nibble Bit 0/Transmit Reference Generator Framing Pulse.
Bit 0
is the least significant bit in the nibble and is the last bit received. The active
low TFOUT signal is synchronous with the first bit in the frame.
Receive Nibble Clock/Receive Serial Clock.
The nibble and serial clocks are
derived from the line side dual rail/NRZ clock signal (RCK/RCKL). RNC is
gapped during framing pattern, service bit and BIP-4 bit times.
Transmit Nibble Bit 3/Transmit Serial Framing Pulse.
In the nibble-parallel
mode, bit 3 is the most significant bit in the nibble and corresponds to the first
bit transmitted in the nibble. When the terminal interface is serial, the negative
framing pulse is synchronous with the first bit in the frame.
Transmit Nibble Bit 2.
Bit 2 in the 4-bit nibble.
Transmit Nibble Bit 1/Transmit Reference Generator Clock In.
Bit 1 in the
transmit nibble. For a serial interface, the TCIN is used to derive the clock out
(TCOUT), data signal (TDOUT), framing pulse (TFOUT), and gapped clock
signal (TCG).The reference generator signals are provided for multiplexing the
external payload data into the serial frame.
63
RNIB3/RSD
O
64
RNIB2/TDO
UT
O
65
RNIB1/TCG
O
66
RNIB0/TFO
UT
RNC/RSC
O
67
O
53
XNIB3/XSF
I
54
55
XNIB2
XNIB1/TCI
N
I
I
5-17
MT90732
CMOS
Terminal Interface
Pin #
56
Name
XNIB0/XSD
I/O/P
I
Description
Advance Information
Transmit Nibble Bit 0/Transmit Serial Data.
In the nibble-parallel mode, bit 0
is the least significant bit in the nibble. For a serial interface, the input must
consist of all the bits in the frame.
Transmit Clock.
For the terminal side nibble-parallel interface, the XCK is
used for all transmit timing functions, including deriving the nibble output clock
(XNC) and framing pulse (XNF).For the serial interface, this clock may be
derived from the transmit reference generator clock output (TCOUT).
Transmit Nibble Framing Pulse.
The XNF and clock signal (XNC) are pro-
vided for multiplexing nibble data into the E2/E3 Framer from external circuitry.
The negative framing pulse identifies the first bit in the frame.
Transmit Nibble Clock/Transmit Reference Generator Clock Out.
The
XNC is derived from the transmit clock (XCK) and is used as a time base for
clocking data out of the external multiplexer and into the E2/E3 Framer. XNC is
gapped during the framing pattern, service bit and BIP-4 bit times. TCOUT is
derived from the input clock (TCIN), and has the same duty cycle.
57
XCK
I
58
XNF
O
59
XNC/TCOU
T
O
Note: I = Input; O = Output; P = Power
Service Bit Interface
Pin #
9
10
11
27
28
29
Name
ROD
ROC
ROF
TOD
TOC
TOF
I/O/P
O
O
O
I
O
O
Description
Receive Service Data Bits.
These service bits are clocked out of E2/E3
Framer on positive transitions of clock signal (ROC).
Receive Service Bits Clock.
A gapped clock that clocks out the service bits.
The clock is active only for clocking out the receive service data bits(ROD).
Receive Service Bits Framing Pulse.
A positive framing pulse that is syn-
chronous with the first bit in the frame.
Transmit Service Data Bits.
The service bits are clocked into E2/E3 Framer
on positive transitions of clock signal (TOC).
Transmit Service Bits Clock.
A gapped clock that clocks in the service bits.
The clock is active only for clocking in the transmit service data bits (TOD).
Transmit Service Bits Framing Pulse.
A positive framing pulse that is syn-
chronous with the first bit in the frame.
Note: I = Input; O = Output; P = Power
Microprocessor Interface
Pin #
36-43
44
45
Name
AD(7-0)
SEL
ALE
I/O/P
I/O
I
I
Description
Address/Data Bus.
These leads constitute the time-multiplexed address and
data bus for accessing the registers which reside in the E2/E3F.
Select.
A low enables the microprocessor to access the E2/E3F memory map
for control, status, and alarm information.
Address Latch Enable.
An active high signal generated by the microproces-
sor. Used by the microprocessor to hold an address stable during a read/write
bus cycle.
Read.
An active low signal generated by the microprocessor for reading the
registers which reside in the memory map.
46
RD
I
5-18
Advance Information
Microprocessor Interface
Pin #
47
48
Name
WR
RDY
I/O/P
I
O
Description
CMOS
MT90732
Write.
An active low signal generated by the microprocessor for writing to the
registers which reside in the memory map.
Ready.
An active high signal indicating an E2/E3F acknowledgment to the
microprocessor that the addressed memory map location can complete the
data transfer.
Note: I = Input; O = Output; P = Power
Control Interface
Pin #
13
Name
NRZLINE
I/O/P
I
Description
Non-Return to Zero Line Selection.
A high enables an NRZ line input (RP
and TP), and causes the HDB3 decoder/encoder to be bypassed. When low
enables the dual rail interface (RP/RN and TP/TN) and the HDB3
decoder/encoder.
Bit Interleaved Parity - 4.
A high enables the BIP-4 function. In the transmit
direction, the BIP-4 is calculated for data nibbles only, and is sent as the last
nibble in the frame format. In the receive direction, the BIP-4 is calculated for
the data bits only and compared against the received value which is present in
the last four bits of the frame. An output indication (BIP-4E) occurs when one
or more columns do not match.
Mode Control.
The two controls select the operating rate of the E2/E3F
according to the table given below.
14
BIP-4
I
16
15
M1
M0
I
M1
0
0
1
1
19
MICRO
I
M0
0
1
0
1
Recommendation
G.745
G.742
G.753
G.751
Rate (kbit/s)
8448
8448
34368
34368
Microprocessor Mode.
A high enables the microprocessor interface. When
the microprocessor is enabled, the following hardware control leads are dis-
abled. BIP-4, Mode (M0 and M1), Serial I/O (SER), and transmit AIS (TAIS).
Bits are provided in the memory map for controlling these functions.
Serial Interface.
A high selects the bit-serial interface for the terminal side
interface. A low selects the nibble-parallel interface.
Terminal Loopback.
A low enables a transmit to receive loopback at the line
side.
Payload Loopback.
A low enables a receive to transmit loopback at the termi-
nal side in the serial mode of operation only.
Transmit Alarm Indication Signal.
A low causes an all ones signal (AIS) to
be sent in place of a G.7XX frame format.
Loop Timing.
A low enables the loop timing feature. Loop timing disables the
transmit clock and enables the receive clock to be used as the transmit clock.
Force Framing Error.
The errored bit is sent into the framing pattern upon the
high-to-low transition of this pin.
20
21
22
23
24
26
SER
TLBK
PLBK
TAIS
LPT
I
I
I
I
I
I
FORCEFE
5-19
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