HANBit
HMD8M36M18G
32Mbyte(8Mx36) 72-pin FP with Parity MODE 2K Ref. SIMM Design 5V
Part No. HMD8M36M18, HMD8M36M18G
GENERAL DESCRIPTION
The HMD8M36M18G is a 8M x 36bit dynamic RAM high density memory module. The module consists of sixteen
CMOS 4M x 4bit DRAM in 24-pin SOJ packages and two CMOS 4Mx 4bit Quad-CAS DRAM in 28pin SOJ packages
mounted on a 72-pin, double-sided, FR-4-printed circuit board.
A 0.1 or 0.22uF decoupling capacitor is mounted on the
printed circuit board for each DRAM components. The module is a single In-line Memory Module with edge connections
and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single
5V DC power supply and all inputs and outputs are TTL-compatible.
PIN ASSIGNMENT
FEATURES
w
Part Identification
HMD8M36M18---- 2048 Cycles/32ms Ref. Solder Lead
HMD8M36M18G-- 2048 Cycles/32ms Ref. Gold Lead
w
Access times : 50, 60ns
w
High-density 32MByte design
w
Single + 5V
±0.5V
power supply
w
JEDEC standard PDpin and pinout
w
Fast Page with Parity mode operation
w
/CAS-before-/RAS refresh capability
w/RAS-only
and Hidden refresh capability
w
TTL compatible inputs and outputs
w
FR4-PCB design
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
-5
-6
M
14
15
16
17
18
SYMBOL
Vss
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
PIN
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SYMBOL
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
NC
Vcc
A8
A9
NC
NC
DQ26
DQ8
PIN
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
SYMBO
L
DQ17
DQ35
Vss
/CAS0
/CAS2
/CAS3
/CAS1
/RAS0
/RAS1
NC
/WE
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
PIN
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SYMBOL
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
OPTIONS
w
Timing
50ns access
60ns access
w
Packages
72-pin SIMM
MARKING
PRESENCE DETECT PINS
(Optional)
Pin
PD1
PD2
PD3
PD4
50ns
NC
Vss
Vss
Vss
60ns
NC
Vss
NC
NC
SIMM
TOP VIEW
PERFORMANCE RANGE
Speed
5
6
tRAC
50ns
60ns
tCAC
13ns
15ns
tRC
90ns
110ns
Note: A11 is used for only 4K Ref.
URL:www.hbeoc.kr
REV.1.0 (August.2002)
-1-
HANBit Electronics Co.,Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
HMD8M36M18G
/CAS0
/RAS0
/CAS0
/RAS0
/OE
/W
U2
A0-A10
DQ0
DQ1
DQ2
DQ3
DQ0-3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U11
/W
/CAS0
/RAS1
A0-A10 /OE
/CAS0
/RAS0
/OE /W
U4
A0-A10
DQ0
DQ1
DQ2
DQ3
U13
/W
DQ4-7
/CAS0
/RAS1
A0-A10 /OE
/CAS1
/CAS1
/RAS0
/OE /W
U6
A0-A10
DQ0
DQ1
DQ2
DQ3
U15
/W
A0-A10
DQ9-12
/CAS1
/RAS1
/OE
/CAS1
/RAS0
/OE /W
U8
A0-A10
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ13-16
DQ2
DQ3
U17
/W
/CAS1
/RAS1
A0-A10
/OE
/CAS0
/CAS1
/CAS2
/CAS3
/RAS0
/OE /W
U1
DQ0
DQ1
DQ2
DQ3
DQ8
DQ17
DQ26
DQ35
DQ0
DQ1
DQ2
DQ3
/W
A0-A10
/CAS0
U10
/CAS1
/CAS2
/CAS3
/RAS1
A0-A10 /OE
/CAS2
/CAS2
/RAS0
/OE
DQ3
/CAS2
/RAS0
/OE
DQ3
U3
/W
DQ0
DQ1
DQ2
A0-A10
DQ0
DQ1
DQ2
A0-A10
DQ0
DQ1
DQ2
A0-A10
DQ0
DQ1
DQ2
A0-A10
DQ0
DQ1
DQ18-21
DQ2
DQ3
DQ0
DQ1
DQ22-25
DQ2
DQ3
DQ0
DQ1
DQ27-30
DQ2
DQ3
DQ0
DQ1
DQ31-34
DQ2
DQ3
U12
/W
/CAS2
/RAS1
A0-A10 /OE
U5
/W
U14
/W
/CAS2
/RAS1
A0-A10 /OE
/CAS3
/CAS3
/RAS0
/OE
DQ3
/CAS3
/RAS0
/OE
DQ3
U7
/W
U16
/W
/CAS3
/RAS1
A0-A10 /OE
U9
/W
U18
/W
/CAS3
/RAS1
A0-A10
/OE
Vcc
Vss
0.1uF
or
Capacitor
for each DRAM
HANBit Electronics Co.,Ltd.
0.22uF
/WE
A0-A10
URL:www.hbeoc.kr
REV.1.0 (August.2002)
-2-
HANBit
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
HMD8M36M18G
RATING
-1V to 7.0V
-1V to 7.0V
18W
-55oC to 150oC
Short Circuit Output Current
I
OS
50mA
w
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to V
SS
, TA=0 to 70 o C )
PARAMETER
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
SYMBOL
Vcc
Vss
V
IH
V
IL
MIN
4.5
0
2.4
-1.0
TYP.
5.0
0
-
-
MAX
5.5
0
Vcc+1
0.8
UNIT
V
V
V
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
I
CC1
-6
I
CC2
I
CC3
-6
-5
I
CC4
-6
I
CC5
I
CC6
-6
I
l(L)
I
O(L)
V
OH
V
OL
I
CC1
: Operating Current * (/RAS , /CAS , Address cycling @t
RC
=min.)
I
CC2
: Standby Current ( /RAS=/CAS=V
IH
)
I
CC3
: /RAS Only Refresh Current * ( /CAS=V
IH
, /RAS, Address cycling @t
RC
=min )
URL:www.hbeoc.kr
REV.1.0 (August.2002)
SPEED
-5
MIN
-
-
-
-
-
-
-
-
-
-
-90
-10
2.4
-
MAX
1008
918
36
1008
918
828
738
18
1008
918
90
10
-
0.4
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
Don't care
-5
Don't care
-5
-3-
HANBit Electronics Co.,Ltd.
HANBit
I
CC4
: Fast Page Mode Current * (/RAS=V
IL
, /CAS, Address cycling @t
PC
=min )
I
CC5
: Standby Current (/RAS=/CAS=Vcc-0.2V )
I
CC6
: /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t
RC
=min )
I
IL
: Input Leakage Current (Any input 0V
≤
V
IN
≤
6.5V, all other pins not under test = 0V)
I
OL
: Output Leakage Current (Data out is disabled, 0V
≤
V
OUT
≤
5.5V
V
OH
: Output High Voltage Level (I
OH
= -5mA )
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA )
HMD8M36M18G
*
NOTE:
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the
output open. I
CC
is specified as an average current. In I
CC1
and I
CC3
, address cad be changed maximum once
while /RAS=V
IL
. In I
CC4
, address can be changed maximum once within one page mode cycle.
o
CAPACITANCE
( T
A
=25 C, Vcc = 5V, f = 1Mz )
DESCRIPTION
SYMBOL
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ1
MIN
-
-
-
-
-
MAX
110
130
80
40
25
UNITS
pF
pF
pF
pF
pF
Input Capacitance [A0-A11(A10)]
Input Capacitance (/W)
Input Capacitance (/RAS0)
Input Capacitance (/CAS0-/CAS3)
Input/Output Capacitance (DQ0-31)
AC CHARACTERISTICS
( 0 C
≤
T
A
≤
70oC , Vcc = 5V±10%, See notes 1,2.)
-5
-6
UNIT
MIN
MAX
MIN
110
50
13
25
3
3
2
30
50
13
50
13
20
15
5
0
10
10K
37
25
10K
13
50
3
3
2
40
60
15
60
15
20
15
5
0
10
10K
45
30
10K
13
50
60
15
30
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HANBit Electronics Co.,Ltd.
o
STANDARD OPERATION
Random read or write cycle time
Access time from /RAS
Access time from /CAS
Access time from column address
/CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
/RAS precharge time
/RAS pulse width
/RAS hold time
/CAS hold time
/CAS pulse width
/RAS to /CAS delay time
/RAS to column address delay time
/CAS to /RAS precharge time
Row address set-up time
Row address hold time
URL:www.hbeoc.kr
REV.1.0 (August.2002)
SYMBOL
t
RC
t
RAC
t
CAC
t
AA
t
CLZ
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
90
-4-
HANBit
Column address set-up time
Column address hold time
Column Address to /RAS lead time
Read command set-up time
Read command hold referenced to /CAS
Read command hold referenced to /RAS
Write command hold time
Write command hold referenced to /RAS
Write command pulse width
Write command to /RAS lead time
Write command to /CAS lead time
Data-in set-up time
Data-in hold time
Refresh period
Write command set-up time
/CAS setup time (C-B-R refresh)
/CAS hold time (C-B-R refresh)
/RAS precharge to /CAS hold time
Access time from /CAS precharge
/CAS precharge time (Fast page)
/RAS pulse width (Fast page )
/W to /RAS precharge time (C-B-R refresh)
/W to /RAS hold time (C-B-R refresh)
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WCR
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
t
CPA
t
CP
t
RASP
t
WRP
t
WRH
10
50
10
10
200K
0
5
10
5
30
0
10
25
0
0
0
10
50
10
13
13
0
10
64
0
5
0
HMD8M36M18G
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
64
ns
ns
ns
ns
ns
35
10
60
10
10
200K
ns
ns
ns
ns
ns
10
30
0
0
0
10
55
10
15
15
0
15
10
5
NOTES
1.
An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.
V
IH (min)
and V
IL (max)
are reference levels for measuring timing of input signals. Transition times are measured between
V
IH(min)
and V
IL(max)
and are assumed to be 5ns for all inputs.
3.
Measured with a load equivalent to 1TTL loads and 100pF
4.
Operation within the t
RCD(max)
limit insures that t
RAC(max)
can be met. t
RCD(max)
is specified as a reference point only. If t
RCD
is greater than the specified t
RCD(max)
limit, then access time is controlled exclusively by t
CAC
.
5.
Assumes that t
RCD
≥
t
RCD(max)
6. t
AR
, t
WCR
, t
DHR
are referenced to t
RAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
OH
or V
OL
.
8. t
WCS
, t
RWD
, t
CWD
and t
AWD
are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If t
WCS
≥
tWCS(min)
the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-
write cycles.
11. Operation within the t
RAD(max)
limit insures that t
RAC(max)
can be met. t
RAD(max)
is specified as a reference
point only. If t
RAD
is greater than the specified t
RAD(max)
limit. then access time is controlled by t
AA
.
URL:www.hbeoc.kr
REV.1.0 (August.2002)
-5-
HANBit Electronics Co.,Ltd.
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