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FEATURES
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SA9203/5
6/3 X 8 PORT EXPANDER
Six (SA9203) or three (SA9205) 8-Bit
I/O Ports
Each bit of one port independently
programmable as input or output
Five (SA9203) or two (SA9205)
remaining ports can be individually
configured as input or output. (Direction
applicable to all 8 pins of each port.)
One 8-Bit port programmable as either
atched or transparent inputs
Supports byte-wide and bit-wide I/O
port addressing modes on all ports
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Readback of all control and port
registers
Interfaces directly with multiplexed
address and data bus microprocessors/
microcontrollers
Internal address latch
Single +5V power supply
Low power CMOS
Completely static operation
TTL-level compatibility
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FIGURE 1: PIN CONNECTION FOR
DESCRIPTION
The SAMES SA9203/5 Port Expander is a
SA9203
CMOS device suited to microprocessor
based applications requiring input/output
port expansion. The device interfaces very
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
simply to any microcontroller/micro-
60
PA 0
10
59
processor with a multiplexed address/data
PA 1
11
58
PA 2
12
57
bus structure.
PA 3
13
56
PA 4
14
55
The SA9203 includes 8 independently
PA 5
15
54
PA 6
16
53
programmable I/O pins for Port A and Port
PA 7
17
52
SA9203
V DD
18
B to F (5 ports) independently programmable
51
PB 0
19
50
PB 1
20
as I/O. It is packaged in a PCB efficient 68
49
PB 2
21
48
pin PLCC package. The SA9205 includes
PB 3
22
47
PB 4
23
46
8 independently programmable I/O pins for
PB 5
24
45
PB 6
25
44
Port A with Port B and Port C as indepen-
PB 7
26
dently programmable I/O, packaged in a
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
cost effective 44 pin PLCC package.
STB
RST
INT
WR
RD
ALE
CS
A8
V SS
AD 7
AD 6
AD 5
AD 4
AD 3
AD 2
AD 1
AD 0
PC 4
PC 5
PC 6
PC 7
V SS
PD 0
PD 1
PD 2
PD 3
PD 4
PD 5
PD 6
PD 7
DR-01266
PF 7
PF 6
PF 5
PF 4
PF 3
PF 2
PF 1
PF 0
V DD
PE 7
PE 6
PE 5
PE 4
PE 3
PE 2
PE 1
PE 0
PC 0
PC 1
PC 2
PC 3
1/14
4491
PDS039-SA9203/5-001
REV. A
20-08-96
SA9203/5
FIGURE 2: BLOCK DIAGRAM FOR SA9203
STB
ALE
CS
RD
WR
RST
INT
P
µ
Inter
face
POR
A
POR
B
POR
C
POR
D
POR
E
POR
F
PA(7:
PB(7:
PC(7:
PD(7:
PE(7:
PF(7:
CON
PRTA
CON
PRTB
AD(7:0
DR-01267
FIGURE 3: PIN CONNECTION FOR SA9205
AD 7
AD 5
V SS
AD 4
AD 1
41
6
5
4
3
2
1
44
AD 3
NC
CS
43
AD 2
42
AD 0
40
AD 6
ALE
RD
WR
INT
RST
V DD
STB
PA 0
PA 1
PA 2
PA 3
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
39
38
37
36
35
PC 7
PC 6
PC 5
PC 4
PC 3
V DD
PC 2
PC 1
PC 0
PB 7
PB 6
SA9205
34
33
32
31
30
29
PB 1
PB 2
PA 7
PB 0
V SS
PA 4
PA 5
PB 3
DR-01268
2/14
sames
PB 4
PB 5
PA6
SA9203/5
FIGURE 4: BLOCK DIAGRAM FOR SA9205
STB
ALE
CS
RD
WR
RST
INT
µ
P
Inter-
face
CON
PRTA
PORT
C
PC(7:0)
PORT
B
PB(7:0)
PORT
A
PA(7:0)
AD(7:0)
CON.
PRTBC
DR-01269
ABSOLUTE MAXIMUM RATINGS*
(All voltages are with respect to VSS)
Parameter
Supply Voltage
Voltage on any pin
Current at any pin
Storage Temperature
Operating Temperature
Symbol
V
DD
-V
SS
V
M
I
M
T
STG
T
O
Min
V
SS
V
SS
-0.3
-40
0
Max
7,0
V
DD
+0.3
100
+125
+70
Unit
V
V
mA
°C
°C
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only. Functional operation of the device
at these or any other condition above those indicated in the operational sections of this
specification, is not implied. Exposure to Absolute Maximum Ratings for extended
periods may affect device reliability.
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SA9203/5
ELECTRICAL CHARACTERISTICS
(All measurements with respect to VSS, at 25°C, unless otherwise specified)
Parameters
Supply Voltage
Static Current
Dynamic Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Tristate Leakage Current
Note 1:
Symbol
V
DD
I
DDS
I
DDD
V
IH
V
IL
V
OH
V
OL
I
IN
I
TL
2.0
1.0
4.5
4.7
0.25 0.5
<1.0 3.0
<1.0 3.0
Min
4.75
Typ Max
5.0 5.25
15
50
20
Unit
V
µA
mA
V
V
V
V
µA
µA
Condition
VDD = 5.0V
(See Note1)
VDD = 5.0V
VDD = 5.0V
VDD = 5.0V
VDD = 5.0V
I
OH
= 5mA
VDD = 5.0V
I
OH
= 5mA
VDD = 5.0V
VDD = 5.0V
All inputs tied to VDD or VSS with outputs not loaded.
Measurements made after RST applied.
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SA9203/5
PIN DESCRIPTION for SA9203
Pin
Type Designation
18,52
VDD
1,35
VSS
61..68 I/O AD0..AD7
Description
+5V Supply Input
0V ground Reference
3-state address/data lines that interface with the CPU
lower 8-bit address/data bus. The 8-bit address is
latched into the SA9203 internal address latch on the
falling edge of ALE. The 8-bit data is respectively
written into and read out of the SA9203 on WR and RD
signals.
Not connected.
Active low input signal used to select the device.
This control signal latches the address on the AD0..7
lines on the falling edge of ALE.
Input low on this line enables the data bus buffers.
Input low on this line causes the data on the address/
data bus to be written to the I/O ports and, control
registers.
If enabled via A.6, this output will be set (active edge
polarity programmed by D6 and output polarity
programmed via D7 of the Port B-F direction control
register) after data has been latched into PORT A.
Input low on this line resets the chip and all internal
registers and all ports to input mode (The register
contents after a reset pulse will be described later).
Input data on PORT A pins will be latched when STB is
active and transparent otherwise (polarity programmed
by D5 of the Port B-F direction control register)
8 general purpose I/O pins comprising PORT A. This
port supports individual input or latched output
configuration of each pin. In addition,each pin of PORT
A selected as an input can be programmed to be
latched or transparent.
8 general purpose I/O pins comprising PORT B. All 8
pins are programmed to be either latched outputs or
transparent inputs.
Identical to PORT B
Identical to PORT B
Identical to PORT B
Identical to PORT B
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2
3
4
5
6
I
I
I
I
N/C
CS
ALE
RD
WR
7
O
INT
8
I
RST
9
I
STB
10..17
I/O
PA0..PA7
19..26
I/O
PB0..PB7
27..34
36..43
44..51
53..60
I/O
I/O
I/O
I/O
PC0..PC7
PD0..PD7
PE0..PE7
PF0..PF7
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