Overall Features ......................................................................................................................................................9
PCI Features ...........................................................................................................................................................9
ATA Features ........................................................................................................................................................10
Other Features ......................................................................................................................................................10
1.9 PCI Bus Operations.................................................................................................................................. 12
1.10 PCI Configuration Space ....................................................................................................................... 13
1.11 Deviations from the Specification ........................................................................................................ 13
Auto-Initialization from FLASH ............................................................................................................... 43
Auto-Initialization from EEPROM............................................................................................................ 44
PCI Configuration Space ......................................................................................................................... 46
Device ID – Vendor ID ...........................................................................................................................................48
PCI Status – PCI Command ..................................................................................................................................48
PCI Class Code – Revision ID ...............................................................................................................................49
BIST – Header Type – Latency Timer – Cache Line Size .....................................................................................50
Base Address Register 0 .......................................................................................................................................50
Base Address Register 1 .......................................................................................................................................50
Base Address Register 2 .......................................................................................................................................51
9.1.8 Base Address Register 3 .......................................................................................................................................51
9.1.9 Base Address Register 4 .......................................................................................................................................51
9.1.10 Base Address Register 5 .....................................................................................................................................52
9.1.11 Subsystem ID – Subsystem Vendor ID................................................................................................................52
9.1.12 Expansion ROM Base Address ...........................................................................................................................53
9.1.16 Software Data Register........................................................................................................................................54
9.1.17 Power Management Capabilities .........................................................................................................................54
9.1.18 Power Management Control + Status ..................................................................................................................55
9.1.19 PCI Bus Master – IDE0........................................................................................................................................55
9.1.23 Data Transfer Mode – IDE0.................................................................................................................................57
9.1.24 Data Transfer Mode – IDE1.................................................................................................................................57
9.1.25 System Configuration Status – Command ...........................................................................................................57
9.1.26 System Software Data Register...........................................................................................................................58
9.1.27 FLASH Memory Address – Command + Status ..................................................................................................58
9.1.32 IDE0 PIO Timing..................................................................................................................................................60
9.1.36 IDE1 PIO Timing..................................................................................................................................................61
9.7 Internal Register Space – Base Address 5................................................................................................ 69
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
9.7.6
9.7.7
9.7.8
9.7.9
9.7.10
9.7.11
9.7.12
9.7.13
9.7.14
9.7.15
PCI Bus Master – IDE0..........................................................................................................................................71
PCI Bus Master – IDE1..........................................................................................................................................73
PCI Bus Master2 – IDE0........................................................................................................................................74
PCI Bus Master2 – IDE1........................................................................................................................................75
PCI Bus Master Byte Count – IDE1 .....................................................................................................................77
FIFO Valid Byte Count and Control – IDE0..........................................................................................................77
FIFO Valid Byte Count and Control – IDE1..........................................................................................................78
System Configuration Status – Command ...........................................................................................................79
System Software Data Register...........................................................................................................................79
FLASH Memory Address – Command + Status ..................................................................................................80
FIFO Port – IDE0.................................................................................................................................................82
FIFO Port – IDE1.................................................................................................................................................83
IDE0 Read Ahead Data .......................................................................................................................................86
IDE0 PIO Timing..................................................................................................................................................90
Test Register – IDE0 ...........................................................................................................................................93
Data Transfer Mode – IDE0.................................................................................................................................94
IDE1 Read/Write Ahead Data ..............................................................................................................................96
IDE1 PIO Timing..................................................................................................................................................99
Test Register – IDE1 .........................................................................................................................................101
Data Transfer Mode – IDE1...............................................................................................................................102
10. Design for Testability ...................................................................................................................103
10.1 Test Mode Register.................................................................................................................................. 104
10.2 NAND Tree Test........................................................................................................................................ 104
10.3 Full Chip Internal Scan ............................................................................................................................ 106
10.4 PLL TEST .................................................................................................................................................. 107
10.4.1 BYPASSING the VCO ...........................................................................................................................................107
10.4.2 TESTING the VCO ................................................................................................................................................107
11.3 Initialization of Controller Channel Timing Registers.......................................................................... 109
NOTE: When using PIO to perform a data transfer, this register only instructs the controller as to whether or not it should
monitor the IORDY signal when the task file data register is accessed. Any value other than 00
H
will cause the controller
to monitor the IORDY signal.............................................................................................................................................110
11.4 Issue ATA Command............................................................................................................................... 110
11.5 IDE PIO Mode Read/Write Operation ..................................................................................................... 110
If no error, repeat the previous four steps until all data for the write command has been transferred or an error has been
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