TECHNICAL DATA
SL74LVU04
Hex Inverter
The 74LVU04 is a low-voltage, Si-gate CMOS device and is pin
compatible with the 74HCU04.
The 74LVU04 is a general purpose hex inverter. Each of the six
inverters is a single stage with unbuffered outputs.
•
•
•
•
Wide Operating Voltage: 1.0÷5.5 V
Optimized for Low Voltage applications: 1.0÷3.6 V
Accepts TTL input levels between V
CC
=2.7 V and V
CC
=3.6 V
Low Input Current
14
1
14
1
N SUFFIX
PLASTIC
D SUFFIX
SOIC
ORDERING INFORMATION
SL74LVU04N
Plastic
SL74LVU04D
SOIC
SL74LVU04
Chip
T
A
= -40° ÷ 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Input
A
L
H
PIN 14 =V
CC
PIN 7 = GND
Output
Y
H
L
SLS
System Logic
Semiconductor
1
SL74LVU04
MAXIMUM RATINGS
*
Symbol
V
CC
I
IK
*
1
I
OK
*
2
I
O
*
3
I
CC
I
GND
P
D
Tstg
T
L
*
Parameter
DC supply voltage (Referenced to GND)
DC input diode current
DC output diode current
DC output source or sink current
-bus driver outputs
DC V
CC
current for types with
- bus driver outputs
DC GND current for types with
- bus driver outputs
Power dissipation per package, plastic DIP+
SOIC package+
Storage temperature
Lead temperature, 1.5 mm from Case for 10 seconds
(Plastic DIP ), 0.3 mm (SOIC Package)
Value
-0.5
÷
+7.0
±20
±50
±25
±50
±50
750
500
-65
÷
+150
260
Unit
V
mA
mA
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SOIC Package: : - 8 mW/°C from 70° to 125°C
1
* : V
I
<
-0.5V or V
I
>
V
CC
+0.5V
*
2
: Vo
<
-0.5V or Vo
>
V
CC
+0.5V
*
3
: -0.5V
<
Vo
<
V
CC
+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced
to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
1.0 V≤V
CC
<2.0 V
2.0 V≤V
CC
<2.7 V
2.7 V≤V
CC
<3.6 V
3.6 V≤V
CC
≤5.5
V
Min
1.0
0
-40
0
0
0
0
Max
5.5
V
CC
+125
500
200
100
50
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
SLS
System Logic
Semiconductor
2
SL74LVU04
V
I
IH
High-Level
Input Leakage
Current
Quiescent
Supply Current
(per Package)
Additional
Quiescent
Supply Current
on input
V
I
= V
ÑÑ
5.5
min
-
max
0.1
min
-
max
1.0
min
-
max
1.0
I
CC
V
I
=0 Â or V
ÑÑ
I
O
= 0 ìA
V
I
= V
ÑÑ
- 0.6V
5.5
-
4.0
-
20
-
40
ìA
I
CC1
2.7
3.6
-
-
0.2
0.2
-
-
0.5
0.5
-
-
-
0.85
0.85
mA
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
LH
=t
HL
= 2.5 ns, R
L
=1 kÙ)
Test
Conditions
V
I
=0 V or
V
1
t
LH
= t
HL
=2.5 ns
Ñ
L
= 50 pF
R
L
= 1 kÙ
V
CC
V
1.2
2.0
2.7
3.0
4.5
Min
-
-
-
-
-
Guaranteed Limit
25°C
max
70
22
16
13
11
-40°C
÷
85°C
min
-
-
-
-
-
max
80
26
19
15
13
-40°C
÷
125°C
min
-
-
-
-
-
max
100
31
23
18
16
ns
Unit
Symbol
Parameter
t
PHL
(t
PLH)
Propagation
Delay, Input A
to Output Y
(Figure 1 )
C
I
C
PD
Input
Capacitance
5.5
-
7.0
-
-
-
-
pF
pF
Power Dissipation Capacitance (Per Inverter)
Ò
À
=25°Ñ, V
I
=0V or V
CC
36
Used to determine the no-load dynamic power consumption:
P
D
= C
PD
V
CC2
f
I
+ (C
L
V
CC2
fo), f
I
- input frequency, fo - output frequency (MHz)
(C
L
V
CC2
fo) – sum of the outputs
SLS
System Logic
Semiconductor
4
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