DATA SHEET
MICRONAS
MAS 35x9F
MPEG Layer 2/3,
AAC Audio Decoder,
G.729 Annex A Codec
June 30, 2004
6251-505-1DS
MICRONAS
MAS 35x9F
Contents
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Section
1.
1.1.
1.2.
1.3.
2.
2.1.
2.2.
2.3.
2.3.1.
2.3.2.
2.3.2.1.
2.3.2.2.
2.4.
2.4.1.
2.4.2.
2.4.2.1.
2.4.2.2.
2.4.2.3.
2.4.2.4.
2.4.3.
2.4.4.
2.5.
2.5.1.
2.5.2.
2.6.
2.6.1.
2.6.2.
2.6.3.
2.7.
2.8.
2.8.1.
2.8.2.
2.8.3.
2.8.4.
2.8.5.
2.8.6.
2.9.
2.10.
2.10.1.
2.10.2.
2.10.2.1.
2.10.2.2.
2.11.
2.11.1.
2.11.2.
2.11.2.1.
Title
Introduction
Features
Features of the MAS 35x9F Family
Application Overview
Functional Description
Overview
Architecture of the MAS 35x9F
DSP Core
RAM and Registers
Firmware and Software
Internal Program ROM and Firmware, MPEG-Decoding
Program Download Feature
Audio Codec
A/D Converter and Microphone Amplifier
Baseband Processing
Bass, Treble, and Loudness
Micronas Bass (MB)
Automatic Volume Control (AVC)
Balance and Volume
D/A Converters
Output Amplifiers
Clock Management
DSP Clock
Clock Output At CLKO
Power Supply Concept
Power Supply Regions
DC/DC Converters
Power Supply Configurations
Battery Voltage Supervision
Interfaces
I2C Control Interface
S/PDIF Input Interface
S/PDIF Output
Multiline Serial Audio Input (SDI, SDIB)
Multiline Serial Output (SDO)
Parallel Input/Output Interface (PIO)
MPEG Synchronization Output
MP3 Block Input Mode
Functional Description of the MP3 Block Input Mode
Setup
Resync Timeout
Detailed Setup
Default Operation
Stand-by Functions
Power-Up of the DC/DC Converters and Reset
Important Advice for Turn-on and Operating Voltage
DATA SHEET
2
June 30, 2004; 6251-505-1DS
Micronas
DATA SHEET
MAS 35x9F
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Section
2.11.3.
2.11.4.
2.11.5.
2.11.6.
3.
3.1.
3.1.1.
3.1.2.
3.1.3.
3.2.
3.2.1.
3.2.2.
3.3.
3.3.1.
3.3.2.
3.3.2.1.
3.3.2.2.
3.3.2.3.
3.3.2.4.
3.3.2.5.
3.3.2.6.
3.3.2.7.
3.3.2.8.
3.3.2.9.
3.3.2.10.
3.3.2.11.
3.3.2.12.
3.3.3.
3.3.4.
3.3.4.1.
3.3.4.2.
3.3.5.
3.3.6.
3.3.7.
3.3.8.
3.4.
3.4.1.
3.4.2.
3.4.3.
3.4.4.
Title
Reset Signal Specification
Control of the Signal Processing
Start-up of the Audio Codec
Power-Down
Controlling
I
2
C Interface
Device Address
I
2
C Registers and Subaddresses
Naming Convention
Direct Configuration Registers
Write Direct Configuration Registers
Read Direct Configuration Register
DSP Core
Access Protocol
Data Formats
Run and Freeze (Codes 0hex to 3hex)
Read Register (Code A
hex
)
Write Register (Code B
hex
)
Read Memory (Codes C
hex
and D
hex
)
Short Read Memory (Codes C4
hex
and D4
hex
)
Write Memory (Codes Ehex and Fhex)
Short Write Memory (Codes E4
hex
and F4
hex
)
Clear SYNC Signal (Code 5hex)
Default Read
Fast Program Download (Code 6
hex
)
Serial Program Download
Read IC Version (Code 7
hex
)
List of DSP Registers
List of DSP Memory Cells
Application Selection and Application Running
Application Specific Control
Ancillary Data
Reading of the Memory Cells “Number of Bits in Ancillary Data” and “Ancillary Data”
DSP Volume Control
Explanation of the G.729A Data Format
Audio Codec Access Protocol
Write Codec Register
Read Codec Register
Codec Registers
Basic MB Configuration
Micronas
June 30, 2004; 6251-505-1DS
3
MAS 35x9F
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Section
4.
4.1.
4.2.
4.3.
4.3.1.
4.3.2.
4.3.3.
4.3.4.
4.3.5.
4.3.6.
4.3.6.1.
4.3.7.
4.3.8.
4.3.9.
4.3.10.
4.3.11.
4.3.12.
4.3.13.
4.3.14.
4.4.
4.5.
4.5.1.
4.6.
4.6.1.
4.6.1.1.
4.6.2.
4.6.2.1.
4.6.2.2.
4.6.2.3.
4.6.2.4.
4.6.2.5.
4.6.2.6.
4.6.2.7.
4.6.2.8.
4.6.3.
4.6.4.
4.6.5.
5.
5.1.
5.2.
6.
Title
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Descriptions
Power Supply Pins
Analog Reference Pins
DC/DC Converters and Battery Voltage Supervision
Oscillator Pins and Clocking
Control Lines
Parallel Interface Lines
PIO Handshake Lines
Serial Input Interface (SDI)
Serial Input Interface B (SDIB)
Serial Output Interface (SDO)
S/PDIF Input Interface
S/PDIF Output Interface
Analog Input Interfaces
Analog Output Interfaces
Miscellaneous
Pin Configuration
Internal Pin Circuits
Reset Pin Configuration for MAS 3529F and MAS 3539F
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Digital Characteristics
I
2
C Characteristics
Serial (I
2
S) Input Interface Characteristics (SDI, SDIB)
Serial Output Interface Characteristics (SDO)
S/PDIF Input Characteristics
S/PDIF Output Characteristics
PIO as Parallel Input Interface: DMA Mode
PIO as Parallel Input Interface:
Program Download Mode
PIO as Parallel Output Interface
Analog Characteristics
DC/DC Converter Characteristics
Typical Performance Characteristics
Application
Typical Application in a Portable Player
Recommended DC/DC Converter Application Circuit
Data Sheet History
DATA SHEET
4
June 30, 2004; 6251-505-1DS
Micronas
DATA SHEET
MAS 35x9F
In MPEG 1 (ISO 11172-3), three hierarchical layers of
compression have been standardized. The most
sophisticated and complex, layer 3, allows compres-
sion rates of approximately 12:1 for mono and stereo
signals while still maintaining CD audio quality. Layer 2
(widely used, e.g., in DVD) achieves a compression of
8:1 without significant losses in audio quality.
The MAS 35x9F supports the “Advanced Audio Cod-
ing” (AAC) that is defined as a part of MPEG 2. AAC
provides compression rates up to 16:1. It defines sev-
eral profiles for different applications. This IC decodes
the “low complexity profile” that is especially optimized
for portable applications.
The MAS 35x9F also implements a voice encoder and
decoder that is compliant to the ITU Standard G.729
Annex A.
SC4 is a proprietary Micronas speech codec technol-
ogy that can be downloaded to the MAS 35x9F, to
allow recording and playing back speech at various
sampling rates.
MPEG Layer 2/3, AAC Audio Decoder,
G.729 Annex A Codec
Release Note: Revision bars indicate significant
changes to the previous edition. This data sheet
applies to the MAS 35x9F version B4.
1. Introduction
The MAS 35x9F is a single-chip, low-power MPEG
layer 2/3 and MPEG2-AAC audio stereo decoder. It
also contains the G.729 Annex A speech compression
and decompression technology for use in memory-
based or broadcast applications. Additional functional-
ity is achievable via download software (e.g., CELP
voice decoder, Micronas SC4 (ADPCM) encoder/
decoder).
The MAS 35x9F decoding block accepts compressed
digital data streams as serial bit streams or in parallel
format, and provides serial PCM and S/PDIF output of
decompressed audio. In addition to the signal process-
ing function, the IC incorporates a high-performance
stereo D/A converter, headphone amplifiers, a stereo
A/D converter, a microphone amplifier, and two DC/DC
converters.
Thus, the MAS 35x9F provides a true
“all-in-one”
solution that is ideally suited for highly optimized mem-
ory-based portable music players with integrated
speech recording and playback function.
Micronas
June 30, 2004; 6251-505-1DS
5
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