MAS 3507D
Contents
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Section
1.
1.1.
1.2.
1.2.1.
1.2.2.
2.
2.1.
2.2.
2.3.
2.4.
2.4.1.
2.4.2.
2.4.3.
2.5.
2.6.
2.6.1.
2.6.2.
2.6.3.
2.6.4.
2.7.
2.7.1.
2.7.2.
2.7.3.
2.7.3.1.
2.7.3.2.
2.7.3.3.
2.7.3.4.
2.7.4.
2.7.4.1.
2.7.4.2.
2.7.4.3.
2.8.
2.8.1.
2.9.
Title
Introduction
Features
Application Overview
Multimedia Mode
Broadcast Mode
Functional Description of the MAS 3507D
DSP Core
Firmware (Internal Program ROM)
Program Download Feature
Baseband Processing
Volume Control / Channel Mixer
Mute / Bypass Tone Control
Bass / Treble Control
Clock Management
Power Supply Concept
Internal Voltage Monitor
DC/DC Converter
Stand-by Functions
Start-up Sequence
Interfaces
MPEG Bit Stream Interface (SDI)
SDI* Selection
Parallel Input Output Interface (PIO)
PIO-DMA Input Mode
Writing MPEG Data to the PIO-DMA
DMA Handshake Protocol
End of DMA Transfer
Audio Output Interface (SDO)
Mode 1: 16 Bits/Sample(I
2
S Compatible Data Format)
Mode 2:32 Bit/Sample (Inverted SOI)
Other Output Modes
Start-up Configuration
Parallel Input Output Interface (PIO)
Status Pins in SDI Input Mode
PRELIMINARY DATA SHEET
2
Micronas
PRELIMINARY DATA SHEET
MAS 3507D
Contents, continued
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Section
3.
3.1.
3.1.1.
3.2.
3.2.1.
3.2.2.
3.3.
3.3.1.
3.3.2.
3.3.3.
3.3.4.
3.3.5.
3.3.6.
3.3.7.
3.3.8.
3.3.9.
3.4.
3.4.1.
3.4.2.
3.4.3.
3.4.4.
3.4.5.
3.4.6.
3.4.7.
3.4.8.
3.4.9.
3.4.10.
3.5.
3.6.
3.6.1.
3.6.2.
3.6.3.
3.7.
3.7.1.
3.7.1.1.
3.7.1.2.
3.7.1.3.
3.7.1.4.
3.7.1.5.
3.7.1.6.
3.7.2.
3.7.2.1.
3.7.2.2.
3.7.3.
Title
Control Interfaces
I
2
C Bus Interface
Device and Subaddresses
Command Structure
The Internal Fixed Point Number Format
Conventions for the Command Description
Detailed MAS 3507D Command Syntax
Run
Read Control Interface Data
Write Register
Write D0 Memory
Write D1 Memory
Read Register
Read D0 Memory
Read D1 Memory
Default Read
Protocol Description
Run Command
Read Control Interface Data
Write to MAS 3507D Register
Write to MAS 3507D D0 Memory
Write to MAS 3507D D1 Memory
Read Register
Read D0 memory
Read D1 memory
Default Read
Write Data to the Control Register
Version Number
Register Table
DC/DC Converter
Muting / Bypass Tone Control
Bass and Treble Control
Memory Area
Status Memory
MPEG Frame Counter
MPEG Status 1
MPEG Status 2
CRC Error Counter
Number Of Ancillary Bits
Ancillary Data
Configuration Memory
PLL Offset for 44/48 kHz Sampling Frequency
Output Configuration
Baseband Volume Matrix
Micronas
3
PRELIMINARY DATA SHEET
MAS 3507D
1.1. Features
– Serial asynchronous MPEG bit stream input (SDI)
– Parallel (PIO-DMA) Input
– Broadcast and multimedia operation mode
– Automatic locking to given data rate in broadcast
mode
MPEG 1/2 Layer 2/3 Audio Decoder
Release Note: Revision bars indicate significant
changes to the previous edition.
This data sheet applies to MAS 3507D version G10
and following versions.
1. Introduction
The MAS 3507D is a single-chip MPEG layer 2/3 audio
decoder for use in audio broadcast or memory-based
playback applications. Due to embedded memories,
the embedded DC/DC up-converter, and the very low
power consumption, the MAS 3507D is ideally suited
for portable electronics.
In MPEG 1 (ISO 11172-3), three hierarchical layers of
compression have been standardized. The most
sophisticated and complex, layer 3, allows compres-
sion rates of approximately 12:1 for mono and stereo
signals while still maintaining CD audio quality. Layer 2
(widely used in DVB, ADR, and DAB) achieves a com-
pression of 8:1 providing CD quality.
In order to achieve better audio quality at low bit rates
(<64 kbit/s per audio channel), three additional sam-
pling frequencies are provided by MPEG 2
(ISO 13818-3). The MAS 3507D decodes both layer 2
and layer 3 bit streams as defined in MPEG 1 and 2.
The multichannel/multilingual capabilities defined by
MPEG 2 are not supported by the MAS 3507D. An
extension to the MPEG 2 layer 3 standard developed
by FhG Erlangen, Germany sometimes referenced as
MPEG 2.5, for extremely low bit rates at sampling fre-
quencies of 12, 11.025, or 8 kHz is also supported by
the MAS 3507D.
– Data request triggered by ’demand signal’ in multi-
media mode
– Output audio data delivered (in various formats) via
an I
2
S bus (SDO)
– Digital volume / stereo channel mixer / Bass / Treble
– Output sampling clocks are generated and con-
trolled internally.
– Ancillary data provided via I
2
C interface
– Status information accessible via PIO pins or I
2
C
– “CRC Error” and “MPEG Frame Synchronization”
Indicators at Pins in serial input mode
– Power management for reduced power consumption
at lower sampling frequencies
– Low power dissipation (30 mW @ f
s
≤
12 kHz,
46 mW @ f
s
≤
24 kHz, 86 mW @ f
s
> 24 kHz @
2.7 V)
– Supply voltage range: 1.0 V to 3.6 V due to built-in
DC/DC converter (1-cell/2-cell battery operation)
– Adjustable power supply supervision
– Power-off function
– Additional functionality achievable via download
software (CELP voice Decoder, ADPCM encoder /
decoder)
CLKI
CLKO
MAS 3507D
Clock
Synthesizer
DC/DC
Converter
/3/
decoded output
/3/
Serial Out
I
2
S
RISC DSP Core
PIO
/8+5/
MPEG 1/2
audio bit stream
/2/
Serial In
serial control
I
2
C
/2/
MPEG frame sync
CRC error
Fig. 1–1:
MAS 3507D block diagram
Micronas
5
FPGA/CPLD
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