SimpliPHY
®
VSC8201
PCB Design and Layout Guide
Single Port 10/100/1000BASE-T
and 1000BASE-X
PHY
Introduction
This purpose of this application note in conjunction with the VSC8201 Datasheet is to provide information to assist in the design and lay-
out of the VSC8201 Gigabit Ethernet Transceiver.
Power Supply Organization and Decoupling
The VSC8201 requires a 3.3v and a 1.5v power supply source for operation using GMII, MII or TBI MAC interfaces. In RGMII and RTBI
modes, an additional 2.5v supply is needed as specified by the RGMI/RTBI standard. The VSC8201 can be powered using the following
options:
•
•
2 separate supplies, 3.3v and 1.5v respectively.
A single 3.3v supply. This is done by using the optional on-chip regulator control circuit, which drives a simple external series pass
type supply regulator (MOSFET) to generate the 1.5v core power supply.
PCB Power Plane Organization
It is recommended that the PCB power plane(s) in a system be divided into four separate regions:
Table 1: Power Supply Plane Regions
PCB Power
Plane
V+IO
V+A33
V+A15
V+DIG
Description
Nominal
Supply Voltage
3.3v/2.5v
3.3v
1.5v
1.5v
8mA
Current
a
Typ
Max
11mA
111mA
48mA
423mA
LQFP Supply Names
b
VDDIO
TXVDD, VDDREC33,
VDDPLL33
VDDREC15, VDDPLL15
VDDDIG
Digital Input/Output
buffer supply
Filtered analog 3.3v
supply
Filtered analog 1.5v
supply
Digital core supply
101mA
41mA
350mA
a. Test conditions: Room temperature (25
o
C), 1000BASE-T data, full duplex, minimum IPG, 64-byte packets, RGMII MAC active, excluding
regulator power dissipation but including external twisted pair termination; all worst case current figures have all nominal power supplies
scaled by +5%.
b. Refer VSC8201 Datasheet to correlate supply names with part pin numbers.
Power Supply Filtering and Decoupling
For best performance, each power supply region should contain capacitors for both bulk decoupling and for local high-frequency decou-
pling. This is summarized in the following tables:
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Table 2: Power Supply Decoupling for separate 3.3v and 1.5v Power Supplies
PCB Power Plane
V+IO
V+A33
V+A15
V+DIG
Bulk Decoupling required
1 pair of 22uF, 1uF
1 pair of 22uF, 1uF and 1 10uF
1 pair of 2.2uF, 1uF
1 pair of 22uF, 1uF
Local Decoupling Required
Four 0.1uF capacitors
Two 0.1 uF capacitors
One 0.1 uF capacitor
Four 0.1uF capacitors
Table 3: Power Supply Decoupling for single 3.3v Supply and Optional fixed 1.5v Regulator
PCB Power Plane
V+IO
V+A33
V+A15
V+DIG
Bulk Decoupling required
1 pair of 22uF, 1uF
1 pair of 22uF, 1uF and 1 10 uF
1 pair of 2.2uF, 1uF
2.2uF
Local Decoupling Required
Four 0.1uF capacitors
Two 0.1uF capacitors
One 0.1 uF capacitor
Four 0.1uF capacitors
The following figure shows the proposed layout for the local decoupling capacitors. The figure is approximately drawn to scale for stan-
dard 0603 size capacitors. Vias to the power and ground planes immediately in the vicinity of the capacitors provide a low inductive path
and aid in heat dissipation.
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Note:Place vias close to or under neath the capacitor pads for
low inductive path and higher heat dissipation rate.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VSC8201
128 LQFP
(Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
0.1 uF
Figure 1: Local High-Frequency decoupling Capacitor Layout - LQFP package
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1
2
3
4
5
6
7
8
9
10
G
C
D
A
B
E
H
.
Note:Place vias close to or under neath the capacitor pads for
low inductive path and higher heat dissipation rate.
K
F
J
0.1 uF
Figure 2: Local High-Frequency decoupling Capacitor Layout - LBGA package
In addition, a ferrite bead should be used to isolate each analog supply from the rest of the board. The bead should be placed in series
between the bulk decoupling capacitors and the local decoupling capacitors.
Figure 3: Power Supply Decoupling Schematic
The beads should be chosen to have the following characteristics:
•
•
Current Rating of at least 150% of the maximum current of the power supply.
Impedance of 80 to 100W at 100Mhz.
Recommended beads are:
•
•
Panasonic EXCELSA39 or similar.
Steward HI 1206N101R-00 or similar.
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Since all PCB designs yield unique noise coupling behavior, not all ferrite beads or decoupling capacitors may be needed for every
design. For this reason, it is recommended that system designers provide and option to replace the ferrite beads with zero-ohm resistors,
once thorough evaluation of system performance is completed.
PCB Chassis ground Region
To isolate the board from the ESD events and to provide a common-mode noise ground path, a separate chassis ground region should
be allocated. This should provide an electrical connection to the external chassis and the shield ground to discharge common-mode
noise through a 75-ohm resistor and a single 1000pF 2kV capacitor. See “VSC8201 System Schematic” in the datasheet.
Figure 4: Ground Plane Layout
Key points
•
•
The chassis ground and the PCB ground should have as much separation as possible. 45 mils or greater is recommended.
There should be no power or ground plane beneath the primary and secondary coils of the transformer.
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VSC8201DL
Regulator Circuit
For systems with a single power supply, the VSC8201 provides an option to generate the 1.5v supply from the 3.3v supply by using the
on chip regulator. The internal regulator is enabled by having a 10k pull-up on the REG_EN pin.
To use the Regulator the following additional components are required:
•
•
FET device, similar to Fairchild FDT439N.
For decoupling, two 0.0047uF capacitors with 10% tolerance or better. NPO, X7R or X5R are all acceptable.
Systems with single 3.3v,+/-10% Wake on LAN supply
The following figure shows the circuit for generating the 1.5v supply using a 3.3v,+/-10% supply
Figure 5: Regulator Circuit using 3.3v, +/-10% supply
Key points
•
•
•
•
Place a 0.0047uF capacitor as close to REG_OUT as possible.
Place a 0.0047uF capacitor as close to the FET as possible.
Tie the GND line together with VREFN, capacitor connected to REF_FILT, resistor R4 (See figure above) and then connect to a com-
mon ground.
VREFP should be connected to the analog 3.3v plane i.e. V+A33.
Using ActiPHY
TM
Power Management
The VSC8201 supports a new power saving mode called ActiPHY
TM
, particularly suited to power saving applications like laptop comput-
ers with wake on LAN capability.
1
When in ActiPHY
TM
mode the PHY is in one of two power down states and has the ability to detect valid signal energy levels at the
media pins and convey it to the station manager.
1. Refer VSC8201 Datasheet.
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