VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC6048
Features
• 8 Fully Integrated Timing Generators for ATE
Applications
• 10/5ns Delay Range, 10ps Resolution
• Fully Digital Interface. No Off-Chip DACs or
Trim Components Required
• ± 4 LSB Differential Non-Linearity
High-Speed Octal
Programmable Timing Generator
• 100MHz/200MHz Dynamic Reprogram Frequency
for Incrementing and Decrementing
• Internal or External High-Speed Clock Option
• Low Power: 8 Watts, max
• Low Cost 160-Pin PQFP Packaging
VSC6048 Block Diagram
CAL_DAT
6
Register
6
SPAN
CAL
DAC
DAC_WR
IN0A
Input
Interleve
IN0B
Variable
Shift
Register
Vernier
Delay
Element
Out 0
400MHz
Clock
800MHz
Clock
3
7
Register
Register
TEST[0:9]
10
Channel 0
Channel 1
Channel 2
7
Channel 7
DIN
ADR[0:2]
DCLK
SHIFT
RCK
RCKN
BYP
FSEL
PLLRST
PLL
Clock Multiplier
Unit
x8, x16
400MHz Clock
Calibration
Register
6
CAL_DAT
800MHz Clock
G52335-0, Rev. 4.0
8/28/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
High-Speed Octal
Programmable Timing Generator
Data Sheet
VSC6048
Functional Description
Reference Clock Selection
Clock multiplication of x8 or x16 may be selected via the FSEL pin, requiring a reference clock of 100
±2.5MHz or 50 ±1.25MHz, respectively. For system applications with 800MHz on board clock, the CMU can
be bypassed by asserting BYP signal and RCK will accept an external 800MHz clock.
In Bypass mode (BYP = 1,
RCK
= 800MHz) the skew from INX to RCK at the pin is 550ps +/-250ps.
Table 1: Reference Clock Selection
BYP
0
0
1
X = don’t care.
FSEL
0
1
X
RCK
100MHz
50MHz
800MHz
Mode of Operations
There are 6 basic modes of operation. These modes are based on two inputs per channel (INA and INB) that
can be interleaved and refire rate. The maximum refire rate for full 10ns span is 100MHz, where the maximum
refire rate for 5ns span is 200MHz. The maximum refire rate at the input to the fine vernier must not be sooner
than 4 cycles of the high-speed clock (800MHz).
Table 2: Suggested Operating Modes
Program Rate
200Mbps
100Mbps
200Mbps
100Mbps
200Mbps
100Mbps
Interleaved
Yes
Yes
No
No
No
No
INA
100MHz
50MHz
200MHz
100MHz
Low
Low
INB
100MHz
50MHz
Low
Low
200MHz
100MHz
TSET[0:9] Range
000 to 1FF
000 to 3FF
000 to 1FF
000 to 3FF
000 to 1FF
000 to 3FF
Data Input (INA, INB)
There are two interleaved inputs per channel. Each input is capable of running at full rate (200MHz). The
input is first retimed off of the internal 400MHz clock generated from the PLL. This means there is a 2.5ns edge
placement window that defines the setup time. This also means that the input pulse must span at least one
400MHz clock edge.
The inputs are low to high edge sensitive. Figure 1 illustrates an equivalent circuit of the input structure for
each channel. Note that the TSET input clock is generated based on the input data.
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52335-0,Rev.4.0
8/28/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC6048
Figure 1: Input Interleave
INxA
High-Speed Octal
Programmable Timing Generator
D
SET Q
TSET_CLK
D
CLR Q
D
SET Q
DATA
INxB
D
SET Q
D
CLR Q
D
CLR Q
400MHz
RCK
PLL
800MHz
FSEL
BYP
Figure 2: Functional Timing Diagram
t
RATETS
TSET[0:9]
t
SETSU
INA
IN
SU
INB
IN
H
t
SETH
OUT
TSET (0000000000)
t
PDTG(MIN)
OUT
TSET (1111111111)
t
OPW
t
PDV(SPAN)
t
PDTG(SPAN)
RCK
Time Set Input (TSET<0:9>)
This is a 10-bit TTL bus that controls the delay value of the vernier. The 3 MSBs control the 800MHz shift
register and the 7 LSBs control the fine delay element. The TSET data is clocked in by a pulse generated from
the input data. The setup time of the TSET data is the same as the input signals (INA, INB). The TSET data
must be stable by the time the input edge arrives at the input pin and data must then be held stable for at least
3.5ns after the input edge arrives at the pin.
G52335-0, Rev. 4.0
8/28/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
High-Speed Octal
Programmable Timing Generator
Figure 3: Fine Vernier Calibration DAC Programming
One Test/Calibration Cycle
Shift Data Into
Calibration Register
SHIFT
1
DCLK
2
3
4
5
6
1
2
3
4
5
6
Hold Data In
Calibration Register
Data Sheet
VSC6048
DIN
5
4
3
2
1
0
X
X
X
X
X
5
4
3
2
1
0
X
X
X
X
DAC_WR
CAL_DAT
(internal)
ADR[2:0]
Vernier 0 DAC Data
Vernier 1 DAC Data
Address for Vernier 0
Address for Vernier 1
DAC Calibration
Each fine vernier must be calibrated to a 1240ps span, one step (10ps) shorter than the 800MHz period
(1.25ns). This is accomplished by setting the fine vernier to maximum delay and adjusting the 6-bit calibration
DAC until the desired range has been achieved.
The calibration data is transferred into the device through a 3-bit serial interface. Refer to Figure 3 for the
programming sequence. Typical DCLK frequencies are 1MHz to 10MHz. Once the calibration value has been
transferred into the device, the data is written into the specified DAC by the rising edge of DCLK when
DAC_WR is HIGH. The address lines must remain stable from the enable of SHIFT to one cycle after the dis-
able of DAC_WR.
DAC Application
There are three DAC_REF pins on this device. Each pin supplies the reference for two or three calibration
DACs. In order to reduce crosstalk between verniers through the DAC_REF supply, it is recommended that
each DAC_REF pin be isolated from each other. This will reduce crosstalk between the the three channel
groups, however, it will not effect crosstalk between verniers within each group.
Table 3: DAC Reference Pin Identification
DAC_REF Pin #
1
18
40
Vernier Channels
0, 1, 2
3, 4
5, 6, 7
Outputs
Each channel has a differential ECL output. The output of the verniers is falling edge active. The shift reg-
ister propagates a 2ns pulse. The fine vernier then stretches the pulse width based on the programmed delay.
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52335-0,Rev.4.0
8/28/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC6048
DC Characteristics
Table 4: Single Ended ECL Inputs and Outputs
Parameter
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
High-Speed Octal
Programmable Timing Generator
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Min
-1020
-2000
-1165
-2000
-
-50
Typ
-
-
-
-
-
-
Max
-700
-1620
-700
-1475
200
-
Units
mV
mV
mV
mV
uA
uA
Conditions
V
IN
= V
IH
(max)
V
IN
= V
IL
(min)
NOTE: V
TT
= -2.0V ± 5%, V
CC
= V
CCA
= GND, R
LOAD
= 50Ω to -2.0V.
Table 5: Differential ECL Inputs and Outputs
Parameter
V
DIFF
V
CM
Description
Input Voltage Differential
Min
200
Typ
-
Max
-
Units
mV
Conditions
Required for full output
swing
Common-mode range
required for full output swing
with V
DIFF
applied
Common-Mode Voltage
-1.5
-
-0.5
V
Figure 4: Differential ECL Input Voltages
Pad
PadN
V
DIFF
/2
V
DIFF
/2
V
CM
G52335-0, Rev. 4.0
8/28/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
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