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VSC9187
VSC9187 Bromley - 3045 x 3045 VT1.5 TSI Switch Fabric
Compliant with SONET Requirements as Stated in ANSI
T1.105 and Bellcore GR-253-CORE
Facilitates Hardware Based UPSR Switching in
Accordance with Telcordia GR-1400-CORE
Thermally Enhanced 360 CCGA Package
IEEE P1149.1 Test Access Port
S P E C I F I C AT I O N S :
F E AT U R E S :
3024x3024 (5 G) Non-Blocking VT1.5 TSI, 6048x6048 (10 Gb/s)
VT1.5 TSI with 2:1 UPSR Input Pre-selection
2x9x622 Mb/s STS-12 LVDS Backplane Inputs with Integrated
Retiming and Alignment
Working and Protection 2 x 9 x 622 Mb/s STS-12 LVDS Outputs
Supports 2:1 Hardware VT1.5 UPSR Selection when used in
Conjunction with VSC9188 VT1.5 Pointer Processor and
Column Aligner
6 Service & 6 Protection STS-1 like Serial 51.84 Mb/s
Interfaces for Local Drop Interfaces
Integrated STS-1 Frame Delay Management on Output for
use in Subtended STS-1 Switch Fabrics
2.5/1.8V Power Supply; 0.18um Technology
A P P L I C AT I O N S :
VT1.5 Time Slot Interchange (TSI)
BENEFITS:
Low cost, low power, VT1.5 switching
K E Y S P E C I F I C AT I O N S :
PARAMETERS
Vdd_core
Vdd_IO
POWER DISSIPATION
IDD_2.5
IDD_1.8
PD_typical
PD_peak
Data STS-12 Inputs I/O
Service Data STS-1 Inputs I/O
STS1 Reference Clock Input
Peak power supply current from 2.5V VDD
Peak power supply current from 1.8V VDD
Typical power dissipation
Peak power dissipation
622Mb/s LVDS
51.84Mb/s LVDS
51.84MHz LVDS
–
–
51.83MHz
0.4 A
2.25 A
4W
5W
–
–
51.85MHz
Nominal
Nominal
Nominal
DESCRIPTION
Voltage for Core
Voltage of IO cells
Min
1.65V
2.3V
Max
1.95V
2.7V
Conditions
Recommended 1.8V
Recommended 2.5V
PB-VSC9187-001
VSC9187
VSC9187 Bromley - 3045 x 3045 VT1.5 TSI Switch Fabric
GENERAL DESCRIPTION:
The VSC9187 is a VT1.5 Time Slot
Interchange (TSI) Device. It provides a
fully non blocking cross connect for 3024
VT1.5's that are all frequency, phase and
column aligned in addition to a pre-
grooming 2:1 UPSR selection. The device receives 9 x 622
Mb/s STS-12 working and protection backplane inputs and
performs all necessary functions to retime and align these
signals from the backplane. VT1.5 tributaries are then pre-
selected with a hardware 2:1 UPSR switch from the working
VSC9187 BLOCK DIAGRAM:
LEG_DI_S[5:0]
LEG_RCLK_S
LEG_RSYN_S
TDM
MUX
[8]
9 x 622Mb/s
STS-12
Serial
Backplane
Inputs
(Service)
MUX
LASB Extraction
[8:0]
STS-1 A1/A2 Output Delay Mgmt (H1/H2)
[8:0]
9 x 622Mb/s
STS-12
Serial
Backplane
Inputs
(Service)
TDM
DEMUX
LEG_DO_S[5:0]
LEG_TCLK_S
LEG_TSYN_S
and protection timeslot with programmable holdover and pre-
hold switch timers. The results of the 2:1 hardware selection
are then made available to an internal 3024x3024 VT1.5 non-
blocking grooming switch, allowing a 5G UPSR ring to be
terminated. Alternatively, the 9 protection STS-12 backplane
inputs can remain unused and the VSC9188 can act as a 5G
VT1.5 switch. Output STS-1 delay management following the
crossconnect allows the VSC9187 to be used in subtended
switch applications with large scale STS-1 crossconnects
such as the VSC9182 40Gb/s STS-1 TSI.
STS_DI_[8:0]
[7:0]
STS_DO_[8:0]
LASB
VT1.5 Hardware UPSR Selection
(Manual or LASB-based)
LEG_DI_P[5:0]
LEG_RCLK_P
LEG_RSYN_P
TDM
MUX
Low-Order Alarm Status Byte (LASB)
Inserted by VSC9188
(contains VTI.5 PM summary)
3024 x 3024 VT1.5 TSI
LEG_DO_P[5:0]
TDM
DEMUX
LEG_TCLK_P
LEG_TSYN_P
[17] MUX
LASB Extraction
9 x 622Mb/s
STS-12
Serial
Backplane
Inputs
(Protection)
[17:9]
STS_DI_[17:9]
[16:9]
[8:0]
LASB
9 x 622Mb/s
STS-12
Serial
Backplane
Outputs
(Protection)
STS_DO_[17:9]
HS-CLK LS-CLK
JTAG Interface
SYNC M-SYNC
CPU Interface
GPO[7:0]
GPI[7:0]
INTB
RSTB
RDB
WRB
CSB
ALE
A[15:0]
D[7:0]
CPU_CLK
System Interface and PLL
Your Partner for Success.
For more information on Vitesse Products visit the Vitesse web site
at www.vitesse.com or contact Vitesse Sales at (800) VITESSE
or sales@vitesse.com
741 Calle Plano
Camarillo, CA 93012, USA
Tel: +1 805.388.3700
Fax: +1 805.987.5896
www.vitesse.com
©2002 Vitesse Semiconductor Corporation
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