VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC830
Features
• Dual 2x2 Crosspoint Switch
• 2.7Gb/s NRZ Data Bandwidth, 2.7GHz Signal
Bandwidth
• PECL/TTL-Compatible Control Inputs
• PECL-Compatible High-Speed I/O
2.7Gb/s Asynchronous
Dual 2x2 Crosspoint Switch
• 50
Ω
Source Terminated Output Driver and
Programmable Input Terminations
• Single 3.3V Supply, 1W Typical Dissipation
• Power-Down Capability for Unused Outputs
• Compact 44-Pin PQFP, 10x10mm Package
General Description
The VSC830 is a monolithic dual 2x2 asynchronous crosspoint switch, designed for critical signal path
control and buffering applications, such as loop-back, protection switching, and multi-channel backplane
driver/receivers. Signal path delay is tightly matched between each output channel to eliminate the need for
delay path compensation when switching between signal sources.
The crosspoint function is based on a multiplexer tree architecture. Each 2x2 switch can be considered as a
pair of 2:1 multiplexers that share the same inputs. The signal path through each switch is fully differential and
delay matched. The signal path is unregistered, so there are no restrictions on the phase, frequency, or signal
pattern at each input. Unused outputs can be independently powered off, thereby eliminating power on unused
sections (see
Design Guide
section in this data sheet). The switch control inputs can be configured to be com-
patible with PECL or TTL levels. The high-speed input and output levels are nominally PECL compatible and
capable of interfacing with a wide range of termination schemes.
VSC830 Symbol Diagram
S1,S2
A1
A2
S1,S2
A1
A2
Y1
Y2
Y1
Y2
G52192-0, Rev 4.0
05/23/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
2.7Gb/s Asynchronous
Dual 2x2 Crosspoint Switch
Data Sheet
VSC830
Functional Block Diagram
PEMODE
S1A
A1A+
A1A-
TERM_ENABLE_A
SL
VCC
VCCP1A
0
Y1A
Y1AN
VEE1A
VCCP2A
1
S2A
SL
A2A+
A2A-
0
Y2A
Y2AN
VEE2A
1
S1B
A1B+
A1B-
SL
VCCP1B
0
Y1B
Y1BN
VEE1B
VCCP2B
SL
1
TERM_ENABLE_B
S2B
0
A2B+
A2B-
Y2B
Y2BN
VEE2B
1
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52192-0, Rev 4.0
05/23/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC830
Functional Description
2.7Gb/s Asynchronous
Dual 2x2 Crosspoint Switch
Select
As shown in Figure 1, each output can be treated as a 2:1 multiplexer, with the A1 and A2 inputs common
to both multiplexers. The select input S1 independently controls the state of the multiplexer that drives output
Y1, and select input S2 independently controls the output of Y2.
Figure 1: Select Functional Block Diagram
S1
S2
A1
A2
Y1
Y2
Table 1 specifies the function of the select inputs.
Table 1: Select Function
S1
0
1
0
1
S2
0
0
1
1
Y1
A1
A2
A1
A2
Y2
A1
A1
A2
A2
MODE
The interface level of the select pins, S1 and S2, can be programmed to either TTL or PECL levels by short-
ing the MODE pin to either V
CC
or V
EE
. Note that the MODE pin must be tied to either V
CC
or V
EE
. The func-
tion of MODE is specified in Table 2.
Table 2: MODE Function
MODE
V
EE
V
CC
S1, S2
TTL
PECL
G52192-0, Rev 4.0
05/23/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
2.7Gb/s Asynchronous
Dual 2x2 Crosspoint Switch
Data Sheet
VSC830
Power-Down
Power to each output stage is provided through V
CC
, V
CCP
, and V
EE
. V
CC
is common to all outputs. To
power off unused outputs, tie the respective V
EE
and V
CCP
pin to V
CC
, as shown in Figure 2.
Figure 2: Power-Down Mode Example
V
CC
V
CCP
1A
V
CCP
2A
V
CCP
1B
V
CCP
2B
V
EE
1A
“ON”
V
EE
2A
“ON”
V
EE
1B
“OFF”
V
EE
2B
“OFF”
Minimum power configuration requires output channel 1A active, so power must be applied to V
CCP
1A
and V
EE
1A at all times.
Programmable input termination
Across each differential input (from the + input to the - input) of the VSC830 is a switched 100
Ω
termina-
tion resistor. Using the TERM_ENABLE pin, the termination can be optionally disabled. To enable the input
termination, connect the respective TERM_ENABLE pin to V
CC
. To disable the internal termination, connect
TERM_ENABLE to V
EE
. If unconnected, the TERM_ENABLE pin will self-bias to V
EE
and disable the inter-
nal termination. Independent termination controls are provided for the “A” and “B” switches.
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52192-0, Rev 4.0
05/23/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC830
AC Characteristics
Table 3: AC Timing
Symbol
F
RATE
F
BW
T
SKW
T
CON
t
R
, t
F
t
jP
Signal path data rate
Signal path bandwidth (-3dB)
Channel to channel delay skew
Switch configuration setup time
(1)
High-speed output rise/fall times, 20% to 80%
Signal path added jitter, peak-peak
(1)
(2)
2.7Gb/s Asynchronous
Dual 2x2 Crosspoint Switch
Parameter
Min
Typ
Max
2.7
2.7
Units
Gb/s
GHz
ps
ns
ps
ps
50
1
150
40
NOTES: (1) Tested on a sample basis only, with 2
23
-1 PRBS data, input signal rise/fall time < 150ps. Value stated in table is added
to measurement system jitter. (2) Input signal rise/fall time < 150ps, measured using an alternating 1, 0 pattern.
DC Characteristics
(
All characteristics are over the specified operating conditions)
Table 4: Power Supply
Symbol
I
CC
P
D
P
T
Parameter
Total V
CC(P)
supply current
Power dissipation per output
(Y1A±, Y2A±, Y1B±, Y2B±)
Total chip power (all outputs powered on)
Min
Typ
Max
350
300
1.2
Units
mA
mW
W
Conditions
NOTE: Specified with outputs terminated, 100Ω between true and complement, V
CC
= 3.45V.
Table 5: Select Input Levels—TTL Mode
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH voltage (TTL)
Input LOW voltage (TTL)
Input HIGH current (TTL)
Input LOW current (TTL)
Min
2.0
Typ
Max
0.8
500
-500
Units
V
V
µA
µA
Conditions
V
IN
= 2.4V
V
IN
= 0.5V
Table 6: Select Input Levels—PECL Mode
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH voltage (PECL)
Input LOW voltage (PECL)
Input HIGH current (PECL)
Input LOW current (PECL)
Min
V
CC
-
1.0
Typ
Max
Units
V
Conditions
V
CC
-
1.6
500
-500
V
µA
µA
V
IN
= 2.5V
V
IN
= 1.5V
Table 7: Control Inputs
Symbol
R
PEMODE
Parameter
PEMODE pin impedance
Min
Typ
3100
Max
Units
Ω
Conditions
G52192-0, Rev 4.0
05/23/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
