VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8140
Features
• 2.48832Gb/s 16-Bit Transceiver
• Targeted for SONET OC-48 / SDH STM-16
Applications
• LVPECL Low-Speed Interface
• On-chip PLL-Based Clock Generator
• High-Speed Clock Output With Power-Down
Option
• Supports Parity at the 16-Bit Parallel Transmit
and Receive Interfaces
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
• Provides Equipment, Facilities and Split Loop-
back Modes as well as Loop Timing Modes
• Loss of Signal (LOS) Detect input
• Meets Bellcore Jitter Performance Specifications
• Single +3.3V Supply
• 2.25 Watts Typical Power Dissipation
• Packages: 128-pin PQFP or 208-pin TBGA
General Description
The VSC8140 is a SONET/SDH compatible transceiver with integrated clock generator for use in SONET/
SDH systems operating at a 2.48832Gb/s data rate. The internal clock generator uses a Phase-Locked Loop
(PLL) to multiply either a 77.76MHz or 155.52MHz reference clock in order to provide the 2.48832GHz clock
for internal logic and output retiming. The 16-bit parallel interface incorporates an on-board FIFO eliminating
loop timing design issues by providing a flexible parallel timing architecture. In addition, the device provides
both facility and equipment loopback modes and two loop timing modes. The VSC8140 operates using a 3.3V
power supply, and is available in either a thermally-enhanced 128-PQFP or a thermally-enhanced 208-pin
TBGA package.
VSC8140 Block Diagram
LOS
POL
RXIN+
RXIN-
RXCLKIN+
RXCLKIN-
D Q
voltage
gen.
Output Register
VREFOUT
VREFIN
RXOUT0
RXOUT15
RXPARITYOUT
RXCLK16O+
RXCLK16O-
EQULOOP
CLK128O+
CLK128O-
RXCLKO_FREQSEL
OVERFLOW
FIFORESET
TXOUT+
TXOUT-
TXCLKOUT+
TXCLKOUT-
FACLOOP
Q D
Divide
by 128
Divide by
16
Divide by
2
RXCLKO16_32+
RXCLKO16_32-
PARMODE
TXCLK16I+
TXCLK16I-
Input Register
TXIN0
Write
Pointer
FIFO
CNTRL
16x5 FIFO
TXIN15
TXPARITYIN
Read
Pointer
Divide by
16
TXCLK16O+
TXCLK16O-
LPTIMCLK+
LPTIMCLK-
LOOPTIM0
2.48832GHz
PLL
PARERR
REFCLK+
REFCLK-
LOOPTIM1
REF_FREQSEL
G52251-0, Rev. 4.0
9/6/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
Data Sheet
VSC8140
Functional Description
Transmitter Low-Speed Interface
The Upstream Device should use the TXCLK16O as the timing source for its final output latch (see Figure
1). The Upstream Device should then generate a TXCLK16I that is phase-aligned with the data. The VSC8140
will latch TXIN[15:0]
±
on the rising edge of TXCLK16I+. The data must meet setup and hold times with
respect to TXCLK16I (see Table 1).
A FIFO exists within the VSC8140 to eliminate difficult system loop timing issues. Once the PLL has
locked to the reference clock, RESET must be held low for a minimum of five CLK16 cycles to initialize the
FIFO, then RESET should be set high and held constant for continuous FIFO operation. For the transparent
mode of operation (no FIFO), simply hold RESET at a constant low state (see Figure 2).
The use of a FIFO permits the system designer to tolerate an arbitrary amount of delay between
TXCLK16O and TXCLK16I. Once RESET is asserted and the FIFO initialized, the delay between TXCLK16O
and TXCLK16I can decrease or increase up to one period of the low-speed clock (6.4ns). Should this delay drift
exceed one period, the write pointer and the read pointer could point to the same word in the FIFO, resulting in
a loss of transmitted data (a FIFO overflow). In the event of a FIFO overflow, an active low OVERFLOW sig-
nal is asserted (for a minimum of five TXCLK16I cycles) which can be used to initiate a reset signal from an
external controller.
The TXCLK16O
±
output driver is a LVPECL output driver designed to drive a 50Ω transmission line. The
transmission line can be DC terminated with a split-end termination scheme (see Figure 3), or DC terminated by
50Ω to V
CC
-2V on each line (see Figure 4). At any time, the equivalent split-end termination technique can be
substituted for the traditional 50Ω to V
CC
-2V on each line. AC-coupling can be achieved by a number of meth-
ods. Figure 5 illustrates an AC-coupling method for the occasion when the downstream device provides the bias
point for AC-coupling.
Figure 1: Low-Speed Systems Interface
OVERFLOW
16 x 5 FIFO
TXCLK16I
write
16
TXCLK16O
read
REFCLK
2.48832GHz
PLL
Div 16
VSC8140
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52251-0, Rev. 4.0
9/6/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8140
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
Figure 2: Enabling FIFO Operation
PLL locked to reference clock.
Minimum 5 CLK16 cycles
FIFO Mode Operation
Transparent Mode Operation
RESET
Holding RESET “low” for a minimum of 5 CLK16 cycles, then setting “high” enables FIFO operation.
Holding RESET constantly “low” bypasses the FIFO for transparent mode operation.
Figure 3: DC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs
VSC8140
V
Split-end equivalent termination is Z
O
to V
TERM
CC
R1 = 125Ω R2 = 83Ω, Z
O
=50Ω, V
TERM
= V
CC
-2V
Z
o
R1
R1
downstream
Z
o
R1||R2 = Z
O
V
CC
R2 + V
EE
R1
R1+R2
= V
TERM
R2
V
EE
R2
Figure 4: DC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs
downstream
VSC8140
Z
o
R1 =50Ω
V
CC
-2V
R1 =50Ω
V
CC
-2V
G52251-0, Rev. 4.0
9/6/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
Data Sheet
VSC8140
Figure 5: AC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs
VSC8140
Z
o
Z
o
50Ω
50Ω
100nF
downstream
bias point
generated
internally
100nF
V
CC
-2V
Receiver Low-Speed Interface
The demultiplexed serial stream is made available by a 16-bit single-ended LVPECL interface
RXOUT[15:0] with accompanying differential LVPECL divide-by-16 clock RXCLK16O
±
and selectable
LVPECL divide-by-16 or -32 clock RXCLK16_32O
±
.
RXCLKO_FREQSEL is used to select RXCLK16_32O
±
. RXCLKO_FREQSEL = “0” designates
RXCLK16_32O± output as 77.76MHz, RXCLKO_FREQSEL = “1” designates RXCLK16_32O± output as
155.52MHz.
The RXCLK16O and RXCLK16_32O output drivers are designed to drive a 50Ω transmission line. The
transmission line can be DC terminated with a split-end termination scheme (see Figure 3), or DC terminated by
50Ω to V
CC
-2V on each line (see Figure 4). AC-coupling can be achieved by a number of methods. Figure 5
illustrates an AC-coupling method for the occasion when the downstream device provides the bias point for
AC-coupling. The divide-by-16 output (RXCLK16O) or the divide-by-16 or -32 output (RXCLK16_32O) can
be used to provide an external looptiming reference clock (after external filtering with a 1x REFCLK PLL) for
the clock multiplication unit on the VSC8140.
The RXOUT[15:0] output drivers are designed to drive a 50Ω transmission line which can be DC termi-
nated with a split-end termination scheme (see Figure 6), or a traditional termination scheme (see Figure 7).
Figure 6: Split-end DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs
Split-end equivalent termination is Z
O
to V
TERM
R1 = 125Ω R2 = 83Ω, Z
O
=50Ω, V
TERM
= V
CC
-2V
V
CC
R1 = 125Ω
VSC8140
Z
o
R1||R2 = Z
o
V
CC
R2 + V
EE
R1
R1+R2
= V
TERM
R2 = 83Ω
V
EE
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52251-0, Rev. 4.0
9/6/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8140
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
Figure 7: Traditional DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs
VSC8140
Z
o
R1 =50Ω
V
CC
-2V
The RXOUT[15:0] output drivers can also be appropriately AC-coupled by a number of methods, how-
ever, DC-coupling is preferred since there is no guarantee of transition density for individual bits in the 16-bit
word. Figure 8 illustrates an AC-coupling method for the occasion when the downstream device provides the
bias point for AC-coupling. Figure 9 illustrates an AC-coupling method for the occasion when the bias point
needs to be generated externally. The resistor values in Figure 9 were selected to generate a bias point of 1.98V,
the mid-point for LVPECL V
OH
and V
OL
as specified for the VSC8140. Resistor values should be selected to
generate the necessary bias point for the downstream device.
Figure 8: AC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs
VSC8140
Z
o
100nF
R1 = 50Ω
V
CC
-2V
downstream
bias point
generated
internally
G52251-0, Rev. 4.0
9/6/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
