VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC6250
Features
• High-Speed Operation:
1 Gb/s Data Rate
500ps min Output Pulse Width
750ps min Input Pulse Width
• Excellent Overall Timing Accuracy:
Ultra-Stable Timing Delays
Minimum Pattern Dependence
Very Fine Timing Resolution (1 LSB = 8ps)
• High Level of Integration Reduces Board Area:
16 Independently Adjustable Delay Lines in a
Single Package
• Configurable as 2 1:8 or 1:16
1Gb/s 16-Channel
Drive-Side Deskew IC
• Wide Span: > 4ns Usable Range
• Pulse Width Adjustment to Compensate for
Dispersion in Pin Electronics:
± 2ns Independent Adjustment of Rising and
Falling Edges
• Fully Digital Single-Chip Solution:
No Off-Chip DACs Required
No DAC-Induced Timing Errors from Analog
Crosstalk, Reference Noise, Temperature, or
Voltage Drift
• Single Power Supply: -2V @ 5W
• 128-Pin PQFP, 14x20mm Thermally-
Enhanced Package
Applications
• Drive-Side Deskew in High-Speed Memory
Testers
• Direct RAMBUS DRAM, SLDRAM, DDR
SDRAM, Fast SSRAM
• High-Speed Instrumentation: Pulse Generators,
Timing Margin Testers for Datalink, Interface,
and Disk Drive Applications
• Telecom, Datacom, and Computer Deskew
General Description
The VSC6250 is intended for use in the next generation of high-speed, high-accuracy memory testers for
devices such as Direct RAMBUS DRAM, SLDRAM, DDR SDRAM, and fast SSRAM.
The VSC6250 provides ultra-precise timing to allow next generation memory testers to achieve excellent
overall timing accuracy. Timing delays of the VSC6250 are extremely stable with respect to temperature and
voltage. Proprietary circuit design and process technology reduce pattern, data, frequency, and duty-cycle
dependencies to an absolute minimum. The VSC6250 requires no external DACs, which eliminates errors due
to DAC reference noise and analog crosstalk, and DAC temperature and voltage drift. The VSC6250 is avail-
able in a 128-pin PQFP, 14x20mm thermally-enhanced package.
G52197-0, Rev. 4.0
8/19/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
1Gb/s 16-Channel
Drive-Side Deskew IC
Data Sheet
VSC6250
VSC6250 Block Diagram
S
R
Output 0
DINA
S
R
Output 7
DIN
S
R
Output 8
DINB
S
R
Output 15
Reference
Clock
(250MHz)
Stability
Control
Parallel Data Interface
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52197-0, Rev. 4.0
8/19/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC6250
Functional Description
1Gb/s 16-Channel
Drive-Side Deskew IC
The VSC6250 is a 1Gb/s 16-channel drive-path deskew IC designed for deskewing differences in path
delay between multiple DUTs in a high-speed memory test system. The VSC6250 can be used as two indepen-
dent 1:8 fanout and deskew sections or as a single 1:16 fanout and deskew. When used as two 1:8 deskews,
input signals are applied to inputs DINA and DINB. When used as a single 1:16 deskew, the input is applied to
input DIN.
The VSC6250 is designed to operate with a conventional 500MHz timing generator which outputs format-
ted pulses to the VSC6250 deskew IC. See Figure 1. The waveform at the input of the VSC6250 is the same as
that presented to the DUT pin. In a memory tester, such a 500MHz timing generator IC may be designed:
• Using one edge to output a single 500Mb/s data stream
• Using two edges to output a single 500Mb/s data stream preceded its complement
• Using three edges to output a single data stream at 500Mb/s surrounded by its complement
• Using two edges to output two interleaved 500Mb/s data streams for an aggregate bandwidth of 1Gb/s.
Formatting is performed inside the timing generator IC. An example interface between the timing generator
IC and the deskew is shown in Figure 1. This configuration is capable of supporting the four different data out-
put choices, with appropriate design of the formatting logic.
The VSC6250 can handle pulses with a data rate up to 1Gb/s or a pulse repetition rate up to 2ns. A timing
diagram for the VSC6250 is shown in Figure 2.
Figure 1: VSC6250 Interface to Timing Generator IC
Timing Generator
VSC6250
Timeset/Dataset
RAM
S
R
Format
Logic
S
R
S
R
Figure 2: VSC6250 AC Timing Diagram
t
REFIRE
DINx
t
PWO
DOUTx
t
PDR
t
PDF
t
PWI
G52197-0, Rev. 4.0
8/19/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
1Gb/s 16-Channel
Drive-Side Deskew IC
Data Sheet
VSC6250
The delay of each of the deskewed outputs can be adjusted separately to compensate for differences in path
length between DUTs on a single test head. The maximum delay is 7ns. Delay span is 5ns. Usable range is a
minimum of 4ns
(1)
. Resolution is 8ps. To compensate for pulse dispersion in pin electronics, delay of the rising
and falling edges can be adjusted independently.
To ensure timing performance, delay of the VSC6250 is measured in production at every time step of every
vernier. Figure 3 shows measured output waveforms of the VSC6250. Figure 3 (a) shows a measured minimum
output pulse width. The specified mimimum output pulse width is 500ps, but this measurement shows operation
down to 300ps. Figure 3 (b) shows typical timing resolution of 8ps.
Figure 3: VSC6250 Measured Output Waveforms
a) Mininum output pulse width of 300ps
(b) Typical timing resolution of 8ps
With next generation testers required to test more DUTs per testhead in the same footprint, board area is a
critical design parameter. Providing 16 deskew channels in a 14mmx20mm thermally-enhanced 128-pin PQFP
package, the VSC6250 consumes less than 1/2 the total board area of the bipolar alternative.
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52197-0, Rev. 4.0
8/19/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC6250
1Gb/s 16-Channel
Drive-Side Deskew IC
The 32 delays (rising and falling edges for 16 channels) in the VSC6250 are programmed using a parallel
interface. Verniers are selected by a 5-bit address word and controlled by two function enable bits. Each vernier
requires 11 bits to set the delay value.
Power dissipation of the VSC6250 is less than 5W from a single -2V supply.
Table 1: Operational Mode Truth Table
Mode #
1
2
Mode Name
Cal Mode
User Mode
CALENN
0
1
Mode Description
Sets timing delays with each vernier selected with ADR [3:0] Serial Data
Input.
Generates timing delays as set by data in Cal Mode.
Figure 4: CAL Mode Timing Diagram
ADR[4:0]
CALENN
D[10:0]
MSB
LSB
Don’t Care
10
9
Load Calibration Register
Data Latch Transparent
Latch Data into Data Latch
Measure Delay
1 CAL Cycle
G52197-0, Rev. 4.0
8/19/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
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