Austin Semiconductor, Inc.
1M x 1 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-92316
• MIL-STD-883
MT5C1001
Limited Availability
PIN ASSIGNMENT
(Top View)
SRAM
28-Pin DIP (C)
(400 MIL)
A10
A11
A12
A13
A14
A15
NC
A16
A17
A18
A19
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A9
A8
A7
A6
A5
A4
NC
A3
A2
A1
A0
D
CE\
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
CE\
FEATURES
•
•
•
•
•
•
•
High Speed: 20, 25, 35, and 45
Battery Backup: 2V data retention
Low power standby
Single +5V (+10%) Power Supply
Easy memory expansion with CE\ and OE\ options.
All inputs and outputs are TTL compatible
Three-state output
32-Pin Flat Pack (F)
OPTIONS
• Timing
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Package(s)
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
MARKING
-20
-25
-35
-45
-55*
-70*
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
CE\
C
EC
F
DCJ
No. 109
No. 207
No. 303
No. 501
GENERAL DESCRIPTION
The MT5C1001 employs low power, high-performance
silicon-gate CMOS technology. Static design eliminates the
need for external clocks or timing strobes while CMOS circuitry
reduces power consumption and provides for greater
reliability.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE|) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (I
SBC2
) over the standard
version.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
• Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C1001
Rev. 2.1 06/05
1
Austin Semiconductor, Inc.
MT5C1001
Limited Availability
SRAM
FUNCTIONAL BLOCK DIAGRAM
V
CC
Vss
A
6
A
5
ROW DECODER
1,048,576-BIT
MEMORY ARRAY
512 rows x 2048
columns
D
A
3
A
15
A
14
A
13
A
8
A
7
I/O CONTROL
A
4
Q
CE\
WE\
POWER
DOWN
COLUMN DECODER
A
2
A
1
A
16
A
0
A
17
A
18
A
19
A
10
A
9
A
12
A
11
TRUTH TABLE
MODE
STANDBY
READ
WRITE
CE\
H
L
L
WE\
X
H
L
OUTPUT
HIGH-Z
Q
HIGH-Z
POWER
STANDBY
ACTIVE
ACTIVE
PIN ASSIGNMENTS
PIN
A
0
-A
19
WE\
CE\
D
Q
NC
V
CC
V
SS
ASSIGNMENT
Address Inputs
Write Enable
Chip Enable
Data Input
Data Output
No Connection
+5V Power Supply
Ground
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Input Relative to Vss................................-.5V to +7V
Voltage on Vcc Supply Relative to Vss...............................-.5V to +7V
Voltage Applied to Q............................................................-.5V to +6V
Storage Temperature......................................................-65
o
C to +150
o
C
Power Dissipation..............................................................................1W
Short Circuit Output Current.........................................................20mA
Lead Temperature (soldering 10 seconds)....................................+260
o
C
Junction Temperature..................................................................+175
o
C
MT5C1001
Limited Availability
SRAM
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
CONDITIONS
SYMBOL
V
IH
V
IL
IL
I
IL
O
V
OH
V
OL
MIN
2.2
-0.5
-5
-5
2.4
MAX
VCC+0.5
0.8
5
5
0.4
UNITS
V
V
µA
µA
V
V
1
1
NOTES
1
1, 2
0V
≤
V
IN
≤
VCC
Output(s) disabled
0V < V
OUT
< VCC
I
OH
= -4.0mA
I
OL
= 8.0mA
PARAMETER
Power Supply
Current: Operating
CONDITIONS
CE\ < V
IL
; V
CC
= MAX
f = MAX = 1/t
RC
(MIN)
Output Open
CE\ > V
IH
; V
CC
= MAX
f = MAX = 1/t
RC
(MIN)
Output Open
CE\ > V
IH
; All Other Inputs
< V
IH
or > V
IH
, V
CC
= MAX
f = 0 Hz
CE\ > V
CC
-0.2V; V
CC
= MAX
V
IL
< V
SS
+0.2V
V
IH
> V
CC
-0.2V; f = 0 Hz
"L" Version Only
SYM
I
cc
-20
125
MAX
-25
-35
120
115
-45
110
UNITS NOTES
mA
3
Power Supply
Current: Standby
I
SBT1
50
45
40
35
mA
I
SBT2
25
25
25
25
mA
I
SBC2
I
SBC2
10
5
10
5
10
5
10
5
mA
mA
CAPACITANCE
PARAMETER
Input Capacitance (A3-A5, A15 -A17)
Output Capactiance (Q)
Input Capacitance: (All Other Inputs)
T
A
= 25 C, f = 1MHz
V
CC
= 5V
o
CONDITIONS
SYMBOL
C
I
Co
C
I
MAXIMUM
10
8
8
UNITS
pF
pF
pF
NOTES
4
4
4
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
Austin Semiconductor, Inc.
MT5C1001
Limited Availability
SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
WRITE CYCLE
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
-20
-25
-35
-45
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
20
15
15
0
1
15
8
0
3
0
9
0
20
25
16
16
0
1
16
10
0
3
0
10
3
3
8
0
25
35
20
20
0
1
20
13
0
3
0
13
20
20
20
3
3
10
0
35
45
25
25
0
1
25
15
0
3
0
13
25
25
25
3
3
15
0
45
35
35
35
3
3
15
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
4, 6, 7
4, 6, 7
4, 6, 7
4
4
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
MT5C1001
Limited Availability
SRAM
167Ω
Q
30pF
V
TH
= 1.73V Q
167Ω
5pF
V
TH
= 1.73V
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
LZCE
, t
LZWE
, t
LZOE
, t
HZCE
, t
HZOE
and t
HZWE
are
specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
4.
5.
6.
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
and
t
HZOE
is less than t
LZOE
.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. t
RC
= Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CONDITIONS
CE\ > (V
CC
- 0.2V)
and
V
IN
> (V
CC
- 0.2V)
or < 0.2V
SYMBOL
V
DR
I
CCDR
V
CC
= 2V
V
CC
= 3V
t
MIN
2
MAX
--
1.0
1.5
UNITS
V
mA
mA
ns
NOTES
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CDR
t
0
--
t
4
4, 11
R
RC
ns
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
CDR
DATA RETENTION MODE
4.5V
V
DR
> 2V
4.5V
t
R
V
DR
CE\
V
IH
V
IL
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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DON’T CARE
UNDEFINED
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