www.fairchildsemi.com
TMC2250A
Matrix Multiplier
12 x 10 bit, 50 MHz
Features
• Four user-selectable filtering and transformation
functions:
– Triple dot product (3 x 3) matrix multiply
– Cascadeable 9-tap systolic FIR filter
– Cascadeable 3 x 3-pixel image convolver
– Cascadeable 4 x 2-pixel image convolver
• 50 MHz (20ns) pipelined throughput
• 12-bit input and output data, 10-bit coefficients
• 6-bit cascade input and output ports in all filter modes
• Onboard coefficient storage, with three-cycle updating of
all nine coefficients
Applications
•
•
•
•
•
•
•
Image filtering and manipulation
Video effects generation
Video standards conversion and encoding/decoding
Three-dimensional image manipulation
Medical image processing
Edge detection for object recognition
FIR filtering for communications systems
Description
The TMC2250A is a flexible high-performance nine-multiplier
array VLSI circuit which can execute a cascadeable 9-tap
FIR filter, a cascadeable 4 x 2 or 3 x 3-pixel image convolu-
tion, or a 3 x 3 color space conversion. All configurations
offer throughput at up to the maximum guaranteed 50 MHz
clock rate with 12-bit data and 10-bit coefficients. All inputs
and outputs are registered on the rising edges of the clock.
The 3 x 3 matrix multiply or color conversion configuration
can perform video standard conversion (YIQ or YUV to
RGB, etc.) or three-dimensional perspective translation at
real-time video rates.
The 9-tap FIR filter configuration, useful in Video, Telecom-
munications, and Signal Processing, features a 16-bit cascade
input to allow construction of longer filters.
The cascadeable 3 x 3 and 4 x 2-pixel image convolver func-
tions allow the user to perform numerous image processing
functions, including static filters and edge detectors. The 16-bit
cascade input port facilitates two-chip 50 MHz cubic convo-
lution (4 x 4-pixel kernel).
The TMC2250A is fabricated in a sub-micron CMOS process
and operates at clock speeds of up to 50 MHz over the full
commercial (0°C to 70°C) temperature and supply voltage
ranges. It is available in 120-pin Plastic Pin Grid Array
(PPGA) packages, 120-lead Ceramic Pin Grid Array pack-
age (CPGA), 120-lead PQFP to PPGA package (MPGA) and
120-lead Plastic Quad FlatPack (PQFP). All input and output
signals are TTL compatible.
REV. 1.0.2 10/25/00
PRODUCT SPECIFICATION
TMC2250A
Functional Description
The TMC2250A is a nine-multiplier array with the internal bus
structure and summing adders needed to implement a 3 x 3
matrix multiplier (triple dot product) a cascadeable 9-tap FIR
filter, a 3 x 3-pixel convolver, or a 4 x 2-pixel convolver all in
one monolithic circuit. With a 50MHz guaranteed maximum
clock rate, this device offers video and imaging system
designers a single-chip solution to numerous common image
and signal-processing problems.
The three data input ports (A, B, C) accept 12-bit two's com-
plement integer data, which is also the format for the output
ports (X, Y, Z) in the matrix multiply mode (Mode 00). In the
filter configurations (Modes 01, 10, and 11) the cascade ports
assume 12-bit integer, 4-bit fractional two's complement data
on both input and output. The coefficient input ports (KA,
KB, KC) are always 10-bit two's complement fractional.
Table 1 details the bit weighting of the input and output data
in all configurations.
KA1(1), KB3(4)
Indicates coefficient data stored in the specified one of the
nine onboard coefficient registers KA1 through KC3, as
shown in the block diagram for that mode, input during or
before the specified clock rising edge (x).
X(1), Y(4), Z(6), CASOUT (6)
Indicated data available at that output port t
DO
after that
specified clock rising edge (x). Applies to all output ports
X
11-0
, Y
11-0
, Z
11-0
, and CASOUT
15-0
.
Numeric Format
Table 2 shows the binary weightings of the input and output
ports of the TMC2250A. Although the internal sums of prod-
ucts could grow to 23 bits, in the matrix multiply mode
(Mode 00) the outputs X, Y and Z are rounded to yield 12-bit
integer words. Thus the output format is identical to the input
data format. In the filter configurations (Modes 01, 10, and
11) the cascade output is always half-LSB rounded to 16
bits, specifically 12 integer bits and 4 fractional guard bits,
with no overflow "headroom". The user is of course free to
half-LSB round the output word to any size less than 16 bits
by forcing a 1 into the bit position of the cascade input
immediately below the desired LSB. In all modes, bit
weighting is easily adjusted if desired by applying the same
scaling correction factor to both input and output data words.
If the coefficients are rescaled, the relative weightings of the
CASIN and CASOUT ports will differ accordingly.
Operating Modes
The TMC2250A can implement four different digital filter
architectures. Upon selection of the desired function by the
user (MODE
1-0
), the device reconfigures its internal data
paths and input and output buses appropriately. The output
ports (XC, YC and ZC) are configured in all filter modes a
16-bit Cascade In and Cascade Out ports so that multiple
devices can be connected to build larger filters. These modes
are described individually below. The I/O function configu-
rations for all four modes are shown in Table 1.
Data Overflow
As shown in Table 2, the TMC2250A's matched input and
output data formats accommodate 0dB (unity) gain. There-
fore, the user must be aware of input conditions that could
lead to numeric overflow. Maximum input data and coeffi-
cient word sizes must be taken into account with the specific
algorithm performed to ensure that no overflow occurs.
Definitions
The calculations performed by the TMC2250A in each mode
are also shown below, utilizing the following notation:
A(1), B(5), C(2), CASIN(3)
Indicates the data word presented to that input port during
the specified clock rising edge(x). Applies to all input ports
A
11-0
, B
11-0
, C
11-0
, and CASIN
15-0
.
Table 1. Data Port Formatting by Mode
Mode
00
01
10
11
Inputs
A
11-0
B
11-0
C
11-0
KA
9-0
KB
9-0
KC9-0
A
11-0
A
11-0
A
11-0
A
11-0
B
11-0
C
11-0
KA
9-0
KB
9-0
KC9-0
B
11-0
B
11-0
NC
NC
Inputs/Output
XC
11-0
X
11-0
YC
11-8
Y
11-8
Y
7-4
Y
7-4
NC
NC
NC
Outputs
YC3-0
Y
3-0
ZC
11-0
Z
11-0
KA
9-0
KB
9-0
KC9-0 CASIN
15-4
CASIN
3-0
KA
9-0
KB
9-0
KC9-0 CASIN
15-4
CASIN
3-0
CASOUT
3-0
CASOUT
15-4
CASOUT
3-0
CASOUT
15-4
CASOUT
3-0
CASOUT
15-4
B
11-0
C
11-0
KA
9-0
KB
9-0
KC9-0 CASIN
15-4
CASIN
3-0
2
REV. 1.0.2 10/25/00
FPGA/CPLD
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