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TN5325N8

产品描述N-channel enhancement-mode vertical dmos fets
产品类别分立半导体    晶体管   
文件大小443KB,共2页
制造商Supertex
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TN5325N8概述

N-channel enhancement-mode vertical dmos fets

TN5325N8规格参数

参数名称属性值
是否Rohs认证不符合
零件包装代码SOT-89
包装说明SMALL OUTLINE, R-PSSO-F3
针数4
Reach Compliance Codecompliant
ECCN代码EAR99
其他特性LOGIC LEVEL COMPATIBLE
外壳连接DRAIN
配置SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压250 V
最大漏极电流 (ID)0.316 A
最大漏源导通电阻7 Ω
FET 技术METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码TO-243AA
JESD-30 代码R-PSSO-F3
JESD-609代码e0
元件数量1
端子数量3
工作模式ENHANCEMENT MODE
最高工作温度150 °C
封装主体材料PLASTIC/EPOXY
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)NOT SPECIFIED
极性/信道类型N-CHANNEL
最大功率耗散 (Abs)1.6 W
最大脉冲漏极电流 (IDM)1.5 A
认证状态Not Qualified
表面贴装YES
端子面层Tin/Lead (Sn/Pb)
端子形式FLAT
端子位置SINGLE
处于峰值回流温度下的最长时间NOT SPECIFIED
晶体管应用SWITCHING
晶体管元件材料SILICON
Base Number Matches1

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TN5325
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
BV
DSS
/
BV
DGS
250V
R
DS(ON)
(max)
7.0Ω
V
GS(th)
(max)
2.0V
I
D(on)
(min)
1.2A
Order Number / Package
TO-236AB*
TN5325K1
TO-92
TN5325N3
TO-243AA**
TN5325N8
Product marking for SOT-23:
N3C❋
where
= 2-week alpha date code
* Same as SOT-23. All units shipped on 3,000 piece carrier tape reels.
** Shipped on 2,000 piece carrier tape and reels.
Product marking for TO-243AA
Features
Low threshold – 2.0V max.
Free from secondary breakdown
Low power drive requirement
Low C
ISS
and fast switching speeds
Excellent thermal stability
High input impedance and high gain
Complementary N- and P-channel devices
TN3C❋
Where
= 2-week alpha date code
Advanced DMOS Technology
These enhancement-mode (normally-off) transistors utilize a
vertical DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces devices with
the power handling capabilities of bipolar transistors and with the
high input impedance and positive temperature coefficient inher-
ent in MOS devices. Characteristic of all MOS structures, these
devices are free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where high breakdown
voltage, high input impedance, low input capacitance, and fast
switching speeds are desired.
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Package Options
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*
*
Distance of 1.6 mm from case for 10 seconds.
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
BV
DSS
BV
DGS
±
20V
-55°C to +150°C
300°C
S G D
G
D
S
D
G
S
D
TO-92
TO-243AA
(SOT-89)
TO-236AB
(SOT-23)
Note: See Package Outline section for dimensions.
1

TN5325N8相似产品对比

TN5325N8 TN5325 TN5325N3 TN5325K1
描述 N-channel enhancement-mode vertical dmos fets N-channel enhancement-mode vertical dmos fets N-channel enhancement-mode vertical dmos fets N-channel enhancement-mode vertical dmos fets
是否Rohs认证 不符合 - 不符合 不符合
零件包装代码 SOT-89 - TO-92 SOT-23
包装说明 SMALL OUTLINE, R-PSSO-F3 - CYLINDRICAL, O-PBCY-W3 SMALL OUTLINE, R-PDSO-G3
针数 4 - 3 3
Reach Compliance Code compliant - compliant compliant
ECCN代码 EAR99 - EAR99 EAR99
其他特性 LOGIC LEVEL COMPATIBLE - HIGH INPUT IMPEDANCE HIGH INPUT IMPEDANCE
配置 SINGLE WITH BUILT-IN DIODE - SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压 250 V - 250 V 250 V
最大漏极电流 (ID) 0.316 A - 0.215 A 0.15 A
最大漏源导通电阻 7 Ω - 7 Ω 7 Ω
FET 技术 METAL-OXIDE SEMICONDUCTOR - METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码 TO-243AA - TO-92 TO-236AB
JESD-30 代码 R-PSSO-F3 - O-PBCY-W3 R-PDSO-G3
JESD-609代码 e0 - e0 e0
元件数量 1 - 1 1
端子数量 3 - 3 3
工作模式 ENHANCEMENT MODE - ENHANCEMENT MODE ENHANCEMENT MODE
最高工作温度 150 °C - 150 °C 150 °C
封装主体材料 PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
封装形状 RECTANGULAR - ROUND RECTANGULAR
封装形式 SMALL OUTLINE - CYLINDRICAL SMALL OUTLINE
峰值回流温度(摄氏度) NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
极性/信道类型 N-CHANNEL - N-CHANNEL N-CHANNEL
最大功率耗散 (Abs) 1.6 W - 0.74 W 0.36 W
认证状态 Not Qualified - Not Qualified Not Qualified
表面贴装 YES - NO YES
端子面层 Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 FLAT - WIRE GULL WING
端子位置 SINGLE - BOTTOM DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
晶体管应用 SWITCHING - SWITCHING SWITCHING
晶体管元件材料 SILICON - SILICON SILICON
Base Number Matches 1 - 1 1
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