CAT24C256
EEPROM Serial 256-Kb I
2
C
Description
The CAT24C256 is a EEPROM Serial 256−Kb I
2
C, internally
organized as 32,768 words of 8 bits each.
It features a 64−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I
2
C protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
External address pins make it possible to address up to eight
CAT24C256 devices on the same bus.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.*
Features
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SOIC−8 WIDE
X SUFFIX
CASE 751BE
SOIC−8
X SUFFIX
CASE 751BE
SOIC−8
W SUFFIX
CASE 751BD
UDFN−8
HU4 SUFFIX
CASE 517AZ
•
•
•
•
•
•
•
•
•
•
•
Supports Standard, Fast and Fast−Plus I
2
C Protocol
1.8 V to 5.5 V Supply Voltage Range
64−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
SOIC, TSSOP and UDFN 8−Pad Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
A
0
A
1
A
2
V
SS
1
V
CC
WP
SCL
SDA
SOIC (W, X), TSSOP (Y), UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
PIN FUNCTION
SCL
CAT24C256
SDA
Pin Name
†
A
0
, A
1
, A
2
SDA
SCL
WP
V
CC
V
SS
V
SS
Function
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
A
2
, A
1
, A
0
WP
Figure 1. Functional Symbol
†The exposed pad for the UDFN packages can be left
floating or connected to Ground.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
May, 2018
−
Rev. 15
1
Publication Order Number:
CAT24C256/D
CAT24C256
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
–65 to +150
–0.5 to +6.5
Units
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Notes 3, 4)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
4. The new product revision (E) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when
a single byte has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order
to benefit from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS
−
Mature Product (Rev D)
Symbol
I
CCR
I
CC
I
SB
I
L
V
IL
V
IH
V
OL1
V
OL2
Parameter
Read Current
Write Current
Standby Current
Test Conditions
Read, f
SCL
= 400 kHz
Write, f
SCL
= 400 kHz
All I/O Pins at GND or V
CC
Pin at GND or V
CC
(
V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, and V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified.)
Min
Max
1
3
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
I/O Pin Leakage
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
< 2.5 V, I
OL
= 1.0 mA
−0.5
V
CC
x 0.7
1
2
1
2
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
V
V
V
V
mA
Units
mA
mA
mA
Table 4. PIN IMPEDANCE CHARACTERISTICS
−
Mature Product (Rev D)
Symbol
C
IN
(Note 5)
C
IN
(Note 5)
I
WP
(Note 6)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
V
IN
= 0 V
V
IN
= 0 V
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.3 V
V
IN
< V
IH
, V
CC
= 1.8 V
V
IN
> V
IH
(V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, and V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified.)
Conditions
Max
8
6
130
120
80
1
Units
pF
pF
mA
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
6. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source. The
variable WP input impedance is available only for Die Rev. C and higher.
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CAT24C256
Table 5. D.C. OPERATING CHARACTERISTICS
−
New Product (Rev E)
(Note 7)
(V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Symbol
I
CCR
I
CCW
I
SB
I
L
V
IL1
V
IL2
V
IH1
V
IH2
V
OL1
V
OL2
Parameter
Read Current
Write Current
Standby Current
All I/O Pins at GND or V
CC
Pin at GND or V
CC
2.5 V
≤
V
CC
≤
5.5 V
1.8 V
≤
V
CC
< 2.5 V
2.5 V
≤
V
CC
≤
5.5 V
1.8 V
≤
V
CC
< 2.5 V
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
< 2.5 V, I
OL
= 1.0 mA
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
I/O Pin Leakage
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
−0.5
−0.5
0.7 V
CC
0.75 V
CC
Test Conditions
Read, f
SCL
= 400 kHz/1 MHz
Min
Max
1
3
2
5
1
2
0.3 V
CC
0.25 V
CC
V
CC
+ 0.5
V
CC
+ 0.5
0.4
0.2
V
V
V
V
V
V
mA
Units
mA
mA
mA
Table 6. PIN IMPEDANCE CHARACTERISTICS
−
New Product (Rev E)
(Note 7)
(V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Symbol
C
IN
(Note 8)
C
IN
(Note 8)
I
WP
, I
A
(Note 9)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current, Address Input
Current (A
0
, A
1
, A
2
)
V
IN
= 0 V
V
IN
= 0 V
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.3 V
V
IN
< V
IH
, V
CC
= 1.8 V
V
IN
> V
IH
Conditions
Max
8
6
75
50
25
2
Units
pF
pF
mA
7. The new product Rev E is identified by letter “E” or a dedicated marking code on top of the package.
8. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
9. When not driven, the WP, A
0
, A
1
, A
2
pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source.
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CAT24C256
Table 7. A.C. CHARACTERISTICS
−
Mature Product (Rev D)
(Notes 10, 11)
(V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, and V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified.)
Fast−Plus
V
CC
= 2.5 V
−
5.5 V
T
A
=
−405C
to +855C
Max
400
0.6
1.3
0.6
0.6
0
100
1,000
300
4
4.7
3.5
100
100
0
2.5
5
1
0
2.5
5
1
0.1
100
100
0
1
5
1
0.6
1.3
0.9
50
100
300
300
0.25
0.5
0.50
0.25
0.55
0.25
0.25
0
50
100
100
Min
Max
1,000
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 12)
t
F
(Note 12)
t
SU:STO
t
BUF
t
AA
t
DH
T
i
(Note 12)
t
SU:WP
t
HD:WP
t
WR
t
PU
(Notes 12, 13)
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between
STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL
and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
4
4.7
4
4.7
0
250
Min
Max
100
Min
Fast
10. The product Rev D is identified by letter “D” or a dedicated marking code on top of the package.
11. Test conditions according to “A.C. Test Conditions” table.
12. Tested initially and after a design or process change that affects this parameter.
13. t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 8. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 x V
CC
to 0.8 x V
CC
≤
50 ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source: I
L
= 3 mA (V
CC
≥
2.5 V); I
L
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
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CAT24C256
Table 9. A.C. CHARACTERISTICS
−
New Product (Rev E)
(Notes 14, 15)
(V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Standard
V
CC
= 1.8 V
−
5.5 V
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 16)
t
F
(Note 16)
t
SU:STO
t
BUF
t
AA
t
DH
T
i
(Note 16)
t
SU:WP
t
HD:WP
t
WR
t
PU
(Notes 16, 17)
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between
STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL
and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
0
2.5
5
1
50
50
0
2.5
5
1
0.1
4
4.7
3.5
50
50
0
1
5
1
4
4.7
4
4.7
0
250
1,000
300
0.6
1.3
0.9
50
50
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
0.25
0.5
0.40
Fast
V
CC
= 1.8 V
−
5.5 V
Min
Max
400
0.25
0.45
0.40
0.25
0
50
100
100
Fast−Plus
V
CC
= 2.5 V
−
5.5 V
T
A
=
−405C
to +855C
Min
Max
1,000
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
14. Test conditions according to “A.C. Test Conditions” table.
15. The New product Rev E is identified by letter “E” or a dedicated marking code on top of the package.
16. Tested initially and after a design or process change that affects this parameter.
17. t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
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