SMM105
Preliminary Information
1
(See Last Page)
Single-Channel Supply Voltage Marginer and Active DC Output Controller
FEATURES & APPLICATIONS
•
Extremely accurate (±0.1%) Active
DC Output Control (ADOC
TM
)
•
ADOC Automatically adjusts supply output
voltage level under all DC load conditions
•
Capable of margining supplies with trim inputs
using either positive or negative trim pin control
•
Wide Margin/ADOC range from 0.3V to VDD
•
Uses either an internal or external VREF
•
Operates from any intermediate bus supply
from 8V to 15V and from 2.7V to 5.5V
•
Programmable START and READY pins
•
Two programmable general purpose monitor
sensors – UV and OV with FAULT Output Flag
•
General Purpose 1k EEPROM with Write Protect
•
I
2
C 2-wire serial bus for programming
configuration and monitoring status.
•
28 pad QFN or 25 ball
Ultra
CSP
TM
(Chip-Scale)
package
INTRODUCTION
The SMM105 actively controls the output voltage level
of a DC/DC converter that uses a Trim or VADJ/FB pin
to adjust the output. An Active DC Output Control
(ADOC
TM
) feature is used during normal operation to
maintain extremely accurate settings of supply
voltages and, during system test, to control margining
of the supplies using I
2
C commands. Total accuracy
with a ±0.1% external reference is ±0.2%, and ±0.5%
using the internal reference. The device can margin
supplies with either positive or negative trim pin control
within a range of 0.3V to VDD. The SMM105 supply
can be from 12V, 8V, 5V or 3.3V to as low as 2.7V to
accommodate any intermediate bus supply.
The voltage settings (margin high/low and nominal)
are programmed into nonvolatile memory through the
industry standard I
2
C 2-wire data bus. The I
2
C bus is
also used to enable margin high, margin low, ADOC or
normal operation. When margining, the SMM105 will
check the voltage output of the converter and make
adjustments to the trim pin via a feedback loop to bring
the voltage to the margin setting. A margining status
register is set to indicate that the system is ready for
test. The SMM105 ADOC will continue to monitor and
adjust the channel output at the specified level.
Applications
•
In-system test and control of Point-of-Load
(POL) Power Supplies for Multi-voltage
Processors, DSPs and ASICs
•
Enterprise and edge routers, servers, Storage
Area Networks
SIMPLIFIED APPLICATIONS DRAWING
12VIN (6V to 15V)
3.3/5Vin (2.7V to 5.5V)
12VIN
WP#
SDA
I
2
C
BUS
SCL
A2
A1
A0
VDD_CAP
VM
COMP1
OV
uP/
DSP/
FPGA/
ASIC
TRIM
VDD
TRIM_CAP
FILT_CAP
VIN
DC/DC
Converter
TRIM
ON/OFF
V+
V-
1.2 VIN
GND
SMM105
Internal or
External
Voltage
Reference
COMP2
VREF_CNTL
READY
START
GND
FAULT#
UV
FAULT#
READY
POWER GOOD
Figure 1 – Applications Schematic using the SMM105 Controller to actively control the DC output level
(ADOC) of a DC/DC Converter as well as margin control. The SMM105 can operate over a wide supply range
Note: This is an applications example only. Some pins, components and values are not shown.
© SUMMIT
Microelectronics, Inc. 2005 •
1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897
2068 1.8 09/20/05
www.summitmicro.com
1
SMM105
Preliminary Information
Figure 2 – Example Power Supply Margining using the SMM105. The waveform on the left is margin low to
high from 1.6V to 2.0V and the waveform on the right is margin high to nominal from 2.0V to 1.8V. The ADOC
function guarantees the output level to be within ±0.2% with a ±0.1% external reference. The bottom
waveform is the READY signal indicating margin is complete.
GENERAL DESCRIPTION
The SMM105 is capable of controlling and margining
the DC output voltage of LDOs or DC/DC converters
that use a trim/adjust pin and to automatically change
the level using a unique Active DC Output Control
(ADOC
TM
). The ADOC function is programmable over
a standard 2-wire I
2
C serial data interface and can be
used to set the nominal DC output voltage as well as
the margin high and low settings. The part actively
controls the programmed set levels to maintain tight
control over load variations and voltage drops at the
point of load. The margin range will vary depending on
the supply manufacturer and model but the normal
range is 10% adjustment around the nominal output
setting. However, the SMM105 has the capability to
margin from VREF_CNTL to VDD.
The user can set the desired voltage settings
(nominal, margin high and margin low) into the EE
memory array for the device. Then, volatile registers
are used to select one of these settings. The registers
are accessed over the I
2
C bus.
In normal operation, Active DC Output Control is set to
adjust the nominal output voltage of the converter.
Typical converters have
±2%
accuracy ratings for their
output voltage. Using the Active DC Output Control
feature of the SMM105 can increase the accuracy to
±0.1%.
This high accuracy control of the converter
output voltage is extremely important in low voltage
applications where deviations in power supply voltage
can result in lower system performance. Active DC
Output Control can also be used for margining a
supply during system test or may be turned off by de-
selecting the function in the Control Select Register.
The margin high and margin low voltage settings can
range from 0.3V to VDD around the converters’
nominal output voltage setting depending on the
specified margin range of the DC-DC converter.
When the SMM105 receives the command to margin,
the Active DC Output Control will adjust the supply to
the selected margin voltage. Once the supply has
reached its margined set point, the Ready bit in the
status register will set and the READY pin will go
active. If Active DC Control is disabled, a margined
supply can return to its nominal voltage by writing to
the margin command register.
In order to obtain maximum accuracy, the SMM105
requires an external voltage reference. An external
reference with ±0.1% accuracy will enable an overall
±0.2% accuracy for the device. A configuration option
also exists so that an internal voltage reference can be
used, but with less accuracy. Total accuracy using the
internal reference is ±0.5%. The SMM105 can be
powered from either a 12V or 8V input via an internal
regulator or the VDD input (Figure 3).
The SMM105 has two additional input pins and one
additional output pin. The input pins, COMP1 and
COMP2, are high impedance inputs, each connected
to a comparator and compared against the
VREF_CNTL input or the internal reference (VREF).
Each comparator can be independently programmed
to monitor for UV or OV. When either of the COMP1
or COMP2 inputs are in fault the open-drain FAULT#
output will be pulled low. A configuration option exists
to disable the FAULT# output during margining.
Programming of the SMM105 is performed over the
industry standard I
2
C 2-wire serial data interface. A
status register is available to read the state of the part
and a Write Protect (WP#) pin is available to prevent
writing to the configuration registers and EE memory.
Summit Microelectronics, Inc
2068 1.8 09/20/05
2
SMM105
Preliminary Information
INTERNAL BLOCK DIAGRAM
VREF_CNTL
V
R EF
MUX
R EADY
FA ULT#
CO MP1
O V/UV
V+
V-
O utput
Control
CO MP2
Trim
Drive
TRIM
TRIM _CAP
O V/UV
S TA RT
W P#
A0
A1
A2
SD A
SCL
I
2
C Serial
Interface
12V IN
3.6/5V
Regulator
Supply
Arbitration
Input Voltage
Sensing and
Signal
Conditioning
EE
Configuration
Registers
& M em ory
VM
V DD
VDD_C AP
Figure 3 – SMM105 Controller Internal Block Diagram.
PACKAGE AND PIN CONFIGURATION
28 Pin QFN
Top View
25 Ball
Ultra
CSP
TM
Bottom View
Pin 1
SDA
NC
NC
NC
NC
VDD_CAP
12VIN
Pin 1
SCL
21
20
19
18
17
16
15
A2
SDA VDD_CAP 12VIN
28 27 26 25 24 23 22
SCL
A2
START
A1
READY
A0
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14
SMM105
VDD
TRIM
COMP1
TRIM_CAP
NC
NC
NC
A1
START
A2
A1
A3
NC
A4
VDD
A5
TRIM
B1
READY
B2
A0
B3
NC
B4
C4
NC
B5
C5
NC
COMP1 TRIM_CAP
C1
D1
E1
C2
D2
E2
C3
D3
E3
GND VREF_CNTL FAULT#
D4
VM
D5
NC
WP#
VREF_CNTL
FILT_CAP
FAULT#
COMP2
NC
VM
WP# FILT_CAP COMP2
E4
E5
Summit Microelectronics, Inc
2068 1.8 09/20/05
3
SMM105
Preliminary Information
PIN DESCRIPTIONS
QFN
Pad
Number
28
1
2
4
6
8
10
18
20
14
9
21
7
Ultra
CSP
TM
Ball
Number
A3
A1
A2
B2
C2
E1
E2
C5
B5
E4
D2
B4
D1
Pin
Type
DATA
CLK
I
I
I
I
CAP
CAP
O
I
I
PWR
GND
Pin Name
SDA
SCL
A2
A1
A0
WP#
FILT_CAP
TRIM_CAP
TRIM
VM
VREF_CNTL
VDD
GND
Pin Description
I
2
C Bi-directional data line
I
2
C clock input.
The address pins are biased either to VDD_CAP or GND. When
communicating with the SMM105 over the 2-wire bus these pins
provide a mechanism for assigning a unique bus address.
Write Protect active low input. When asserted, writes to the
configuration registers and general purpose EE are not allowed.
External capacitor input used to filter the VM input.
External capacitor input used for Active Control and margining.
Output voltage used to control and/or margin converter voltages.
Connect to the converter trim input.
Voltage monitor input. Connect to the DC-DC converter positive
sense line or its’ +Vout pin.
Voltage reference input used for DC output control and margining.
VREF_CNTL can be programmed to output the internal 1.25V
reference. Pin should be left open if using VREF internal
Power supply of the part.
Ground of the part. The SMM105 ground pin should be connected
to the ground of the device under control or to a star point ground.
PCB layout should take into consideration ground drops.
12V power supply input internally regulated to either 3.6V or 5.5V.
When using the 3.6V internal regulator option, the 12VIN input can
be as low as 8V. It can be as high as 15V using the 5.5V internal
regulator.
Programmable active high/low input. The START input is used
solely for enabling Active Control and/or margining. There is also
a programmable start delay time, T
START
to delay ADOC/Margin
control.
Programmable active high/low open drain output indicates that VM
is at its set point. When programmed as an active high output,
READY can also be used as an input. When pulled low, it will latch
the state of the comparator inputs.
External capacitor input used to filter the internal supply rail.
COMP1 and COMP2 are high impedance inputs, each connected
internally to a comparator and compared against the VREF_CNTL
input. Each comparator can be independently programmed to
monitor for UV or OV. The monitor level is set externally with a
resistive voltage divider.
When either of the COMP1 or COMP2 inputs are in fault the open-
drain FAULT# output will be pulled low. A configuration option
exists to disable the FAULT# output while the device is margining.
No Connect. Leave floating; do not connect anything to the NC
pins.
2068 1.8 09/20/05
22
A5
PWR
12VIN
3
B1
I
START
5
23
19
12
C1
A4
C4
E3
I/O
CAP
I
I
READY
VDD_CAP
COMP1
COMP2
11
13,15,16
17,24-27
D3
B3,C3,
D4,D5,
E5
O
FAULT#
NC
NC
Summit Microelectronics, Inc
4
SMM105
Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ...................... -55
°
C to 125
°
C
Storage Temperature QFN ................... -65
°
C to 150
°
C
Terminal Voltage with Respect to GND:
VDD Supply Voltage ..........................-0.3V to 6.0V
12VIN Supply Voltage......................-0.3V to 15.0V
All Others ................................-0.3V to V
DD
+ 0.7V
Output Short Circuit Current ............................... 100mA
Junction Temperature.........................…….....…...125°C
ESD Rating per JEDEC……………………..……..2000V
Latch-Up testing per JEDEC………..……......…
±
100mA
Note - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of the specification is
not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability. Devices are
ESD sensitive. Handling precautions are recommended.
RECOMMENDED OPERATING CONDITIONS
Temperature Range (Industrial) .......... –40
°
C to +85
°
C
(Commercial)............ –5
°
C to +70
°
C
VDD Supply Voltage.................................. 2.7V to 5.5V
12VIN Supply Voltage (1)........................ 8.0V to 14.0V
VIN.............................................................GND to VDD
VOUT.......................................................GND to 15.0V
Package Thermal Resistance (θ
JA
)
28 Pad QFN…………….…………………….…80
o
C/W
25 Ball
Ultra
CSP
TM
………..………….…….…TBD
o
C/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
Note 1 – Range depends on internal regulator set to 3.6V or 5.5V, see
12VIN specification below.
DC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min.
Typ.
Max
Unit
VDD
12VIN
VM
I
DD
I
12VIN
I
TRIM
V
ADOC
V
IH
V
IL
V
OL
OV/UV
V
HYST
Supply Voltage
Supply Voltage
Positive Sense Voltage
Power Supply Current from
VDD
Power Supply Current from
12VIN
TRIM output current
through 100Ω to 1.0V
Margin Control/ADOC
Range
Input High Voltage
Input Low Voltage
Programmable Open Drain
Output (READY)
Monitor Voltage Range
Base DC Hysteresis
Internally regulated to 5.5V
Internally regulated to 3.6V
VM pin
All TRIM pins and 12VIN floating
All TRIM pins and VDD floating
TRIM Sourcing Max Current
TRIM Sinking Max Current
Depends on Trim range of DC-
DC Converter
VDD = 2.7V
VDD = 5.0V
VDD = 2.7V
VDD = 5.0V
ISINK = TBD
COMP1 and COMP2 pins
COMP1 and COMP2 pins,
V
TH
-V
TL
– Note 1
-0.3
3
10
1.5
1.5
VREF_CNTL
2.7
10
6
-0.3
3.3
5.5
15
14
VDD
V
V
V
mA
mA
mA
mA
3
3
5
5
VDD
VDD
VDD
0.1xVDD
0.3xVDD
0.2
VDD
V
V
V
V
V
mV
0.9xVDD
0.7xVDD
Note 1 – The Base DC Hysteresis voltage is measured with a 1.25V external voltage source. The resulting value is determined by subtracting
Threshold Low from Threshold High, V
TH
-V
TL
while monitoring the FAULT# pin state. Base DC Hysteresis is measured with a 1.25V input. Actual DC
Hysteresis is derived from the equation: (V
IN
/V
REF
)(Base Hysteresis). For example, if V
IN
=2.5V and V
REF
=1.25V then Actual DC Hysteresis=
(2.5V/1.25V)(0.003V)=6mV.
Summit Microelectronics, Inc
2068 1.8 09/20/05
5
PCB设计
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