SMB113A/B/SMB117/A
High-power, Four-channel Programmable DC-DC System Power Managers
FEATURES & APPLICATIONS
•
Digital programming of all major parameters via
I
2
C interface and non-volatile memory
•
Output voltage set point
•
Input/battery voltage monitoring
•
Output power-up/down sequencing
•
Digital soft-start and output slew rate
•
Dynamic voltage control of all outputs
•
UV/OV monitoring of all outputs
•
Enable/Disable outputs independently
•
User friendly Graphical User Interface (GUI)
•
Four synchronous step-down output channels
•
Integrated RESET monitor
•
+2.7V to +6.0V Input Range
•
Highly accurate output voltage: <1.5%
•
Factory programmable dead times
•
0% to 100% Duty Cycle operation
•
Undervoltage Lockout (UVLO) with hysteresis
•
250kHz (SMB117A), 400kHz (SMB117), 800kHz
(SMB113A), 1MHz (SMB113B) operating frequency
•
96 bytes of user configurable nonvolatile memory
Preliminary Information
INTRODUCTION
The SMB113A/B and SMB117/A are highly integrated and
flexible four-channel power managers designed for use in a
wide range of applications. The built-in digital programmability
allows system designers to custom tailor the device to suit
almost any multi-channel power supply application from digital
camcorders to set-top boxes. Complete with a user friendly
GUI, all programmable settings, including output voltages and
input/output voltage monitoring, can be customized with ease.
The SMB113A/B and SMB117/A integrate all the essential
blocks required to implement a complete four-channel power
subsystem consisting of four synchronous step-down “buck”
controllers. Additionally sophisticated power control/monitoring
functions required by complex systems are built-in. These
include digitally programmable output voltage set point, power-
up/down sequencing, enable/disable, dynamic voltage
management and UV/OV monitoring on all channels.
The integration of features and built-in flexibility of the
SMB113A/B and SMB117/A allows the system designer to
create a “platform solution” that can be easily modified via
software without major hardware changes. Combined with the
re-programmability of the SMB113A/B and SMB117/A, this
facilitates rapid design cycles and proliferation from a base
design to future product generations.
The SMB113A/B and SMB117/A are suited to a wide variety of
applications with an input range of +2.7V to +6.0V. Higher
input voltage operation can easily be implemented with a small
number of external components.
Output voltages are
extremely accurate (<1.5%). Communication is accomplished
2
via the industry standard I C bus. All user-programmed
settings are stored in non-volatile EEPROM of which 96 bytes
may be used as general-purpose memory. The devices are
offered in both the commercial and the industrial operating
temperature range. The package type is a lead-free, RoHS
compliant, 5x5 QFN-32.
Applications
•
•
•
•
•
•
Car & Marine Navigation Systems
Set-top Boxes
TVs
DDR Memory
Mobile Computing/PDAs
Office Equipment
•
DMB Systems
SIMPLIFIED APPLICATIONS DRAWING
+2.7V to +6.0V
or
Li-Ion
SMB113A/B
+0.5V to Vin (Prog.) @ 1.5A/5A
+2.7V to +6.0V
or
Li-Ion
CPU Core
I2C/SMBus
SMB117/A
+0.5V to Vin (Prog.) @ 5A/10A
CPU Core
I2C/SMBus
Enable Input
Reset Input
System
Control
and
Monitoring
4 Step-
Down
(Buck)
Channels
+0.5V to Vin (Prog.) @ 1.5A/5A
Memory, I/O
Enable Input
Reset Input
System
Control
and
Monitoring
+0.5V to Vin (Prog.) @ 1.5A/5A
DSP/Codec
4 Step-
Down
(Buck)
Channels
+0.5V to Vin (Prog.) @ 5A/10A
Memory, I/O
+0.5V to Vin (Prog.) @ 5A/10A
DSP/Codec
RESET Output
(Power Good)
RESET
Monitor
+0.5V to Vin (Prog.) @ 1.5A/5A
Analog/RF
RESET Output
(Power Good)
RESET
Monitor
+0.5V to Vin (Prog.) @ 5A/10A
Analog/RF
Figure 1 – Applications schematic featuring the SMB113A/B/117/A programmable DC-DC controllers.
Note: This is an applications example only. Some pins, components and values are not shown.
© SUMMIT
Microelectronics, Inc. 2007
757 N. Mary Avenue • Sunnyvale CA 94085
Phone 408 523-1000 • FAX 408 523-1266
http://www.summitmicro.com/
2111 2.4 6/24/2008
1
SMB113A/B/SMB117/A
Preliminary Information
GENERAL DESCRIPTION
The SMB113A/B and SMB117/A are fully programmable
DC-DC controllers that incorporate power delivery and
advanced power monitoring and control functionality.
The devices integrate four synchronous “buck” step-
down controllers in a space saving package.
The SMB113A uses a fixed 800kHz whereas the
SMB113B uses a fixed 1MHz, the SMB117 a fixed
400kHz and the SMB117A a fixed 250kHz Pulse Width
Modulation (PWM) control circuit. A type-three voltage
mode compensation network is used offering a cost
effective solution without compromising transient
response performance. By utilizing external N- and P–
type MOSFET transistors the efficiency and load current
level can be customized to fit a wide array of system
requirements.
The SMB113A/B and SMB117/A contain four buck
outputs capable of producing an output voltage less than
the input voltage. Each buck output voltage is set by an
internal resistor divider and a programmable voltage
reference. The integrated resistor divider eliminates the
cost and space necessary for external components and
has several programmable values.
Through the
programmability of the reference and the resistor divider,
practically any output voltage smaller than the battery
can be produced without the need to change external
components.
The SMB113A/B and SMB117/A are capable of power-
on/off cascade sequencing where each channel can be
assigned one of four unique sequence positions. During
sequencing each channel in a given sequencing position
is guaranteed to reach its programmed output voltage
before the channel(s) occupying the next sequence
position initiate their respective soft-start sequence. A
unique programmable delay exists between each power
on/off sequence position. In addition to power on/off
sequencing all supplies can be powered on/off
individually through an I
2
C command or by assertion of
the enable pin.
Each output voltage is monitored for under-voltage and
over-voltage (UV/OV) conditions, using a comparator-
based circuit where the output voltage is compared
against an internal programmable reference.
An
additional feature of the output voltage monitoring is a
programmable glitch filter capable of digitally filtering a
transient OV/UV fault condition from a true system error.
When a fault is detected for a period in excess of the
glitch filter, all supplies may be sequenced down or
immediately disabled and an output status pin can be
asserted.
The current system status is always
accessible via internal registers containing the status of
all four channels.
The SMB113A/B and SMB117/A also possess an
Under-voltage Lockout (UVLO) circuit to ensure the
devices will not power up until the input voltage has
reached a safe operating voltage. The UVLO function
exhibits hysteresis, ensuring that noise or a brown out
voltage on the supply rail does not inadvertently lead to
a system failure.
The SMB113A/B and SMB117/A provide dynamic
voltage management over all of their output voltages.
Through an I
2
C command, all output voltage levels can
be increased or decreased to a pre-programmed level.
In addition, each output is slew rate limited by soft-start
circuitry that is user-programmable and requires no
external capacitors.
All programmable settings on the SMB113A/B and the
SMB117/A are stored in non-volatile registers and are
easily accessed and modified over an industry standard
I
2
C serial bus. For fastest prototype development times
Summit offers an evaluation card and a Graphical User
Interface (GUI).
Summit Microelectronics, Inc.
2111 2.4 6/24/2008
2
SMB113A/B/SMB117/A
Preliminary Information
TYPICAL APPLICATION
VIN: +2.7V to +6.0V
SMB113A/B
(SMB117/A)
VBATT
VDDCAP
GND
HSDRV_CH3
+0.8V to VIN @ 5A (10A)
HVSUP3
LSDRV_CH3
SDA
SCL
PWREN
VM_CH3
COMP1_CH3
COMP2_CH3
HEALTHY/nRESET
HOST_RESET
HVSUP2
HSDRV_CH2
HVSUP0
HSDRV_CH0
+0.8V to VIN @ 5A (10A)
LSDRV_CH2
+0.8V to VIN @ 5A (10A)
LSDRV_CH0
VM_CH2
COMP1_CH2
VM_CH0
COMP1_CH0
COMP2_CH2
HVSUP1
COMP2_CH0
HSDRV_CH1
+0.8V to VIN @ 5A (10A)
LSDRV_CH1
VM_CH1
COMP1_CH1
COMP2_CH1
Figure 2 – Typical application schematic
Summit Microelectronics, Inc
2111 2.4 6/24/2008
3
SMB113A/B/SMB117/A
Preliminary Information
INTERNAL BLOCK DIAGRAM
COMP2_CH[0,1,2,3]
VM_CH[0,1,2,3]
100k
–
+
OA
+
–
CLAMP
MAX LIMIT
LOW LIMIT
DUTY
CYCLE
LIMIT
OSC
Fixed 250/400/
800/1000kHz
HVSUP[0,1,2,3]
Channel 0,1,2,3
Synchronous buck
PWM Converter
HSDRV[0,1,2,3]
I
2
C/SMBUS
SDA
SCL
COMP1_CH[0,1,2,3]
VREF
LEVEL
SHIFTER
DIGITAL TO
ANALOG
CONVERTER
DEADTIME
+
–
GLITCH
FILTER
OVER VOLTAGE
DETECTION
LSDRV[0,1,2,3]
SEQUENCING
AND
MONITORING
LOGIC
ENABLE
PWREN0
+
–
VREF
VREF
GLITCH
FILTER
UNDER VOLTAGE
DETECTION
VBATT
VDDCAP
GND
BANDGAP
VDD_CAP
2.5V
REGULATOR
+
–
UV2
D
Q
LEVEL
SHIFTER
VREF
+
–
UV1
Figure 3 –SMB113A/B and SMB117/A internal block diagram. Programmable functional blocks include: level
shifters, digital to analog converter and the VM_CH[0,1,2,3] voltage dividers.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
4
SMB113A/B/SMB117/A
Preliminary Information
PIN DESCRIPTION
Pin Number
Pin Type
Pin Name
Pin Description
The HSDRV_CH0 (Channel 0 High-side Driver) pin is the upper
switching node of the channel 0 synchronous step-down buck
controller. Attach to the gate of p-channel MOSFET. A delay
exists between the assertion of HSDRV_CH0 and assertion of
LSDRV_CH0 to prevent excessive current flow during switching.
The HEALTHY pin is an open drain output. High when all
enabled output supplies are within the programmed levels.
HEALTHY will ignore any disabled supply.
There is a
programmable glitch filter on the under-voltage and over-voltage
sensors so that short transients outside of the limits will be
ignored by HEALTHY. This pin can also be programmed to act
as a Reset Output (nRESET). In this case, it releases with a
programmable delay after all outputs are valid. When used, this
pin should be pulled high by an external pull-up resistor.
The COMP1_CH0 (Channel 0 primary Compensation) pin is the
primary feedback input of the channel 0 step-down buck
controller. The COMP1_CH0 pin is internally connected to a
programmable resistor divider.
The COMP2_CH0 (Channel 0 secondary Compensation) pin is
the secondary feedback input of the channel 0 step-down buck
controller.
The VM_CH0 (Channel 0 Voltage Monitor) pin connects the
channel 0 step-down controller output. Internally the VM_CH0 pin
connects to a programmable resistor divider.
SDA (Serial Data) is an open drain bi-directional pin used as the
I
2
C data line. SDA must be tied high through a pull-up resistor.
SCL (Serial Clock) is an open drain input pin used as the I
2
C
clock line. SCL must be tied high through a pull-up resistor.
The LSDRV_CH1 (Channel 1 Low-side Driver) pin is the lower
switching node of the channel 1 synchronous step-down buck
controller. Attach to the gate of n-channel MOSFET.
Channel 1 High Voltage Supply for Channel 1 buck driver.
The HSDRV_CH1 (Channel 1 High-side Driver) pin is the upper
switching node of the channel 1 synchronous step-down buck
controller. Attach to the gate of p-channel MOSFET. A delay
exists between the assertion of HSDRV_CH1 and assertion of
LSDRV_CH1 to prevent excessive current flow during switching.
The HOST_RESET pin is an active high reset input. When this
pin is asserted high, the nRESET output will immediately go low.
When HOST_RESET is brought low, nRESET will go high after a
programmed reset delay. When pin 2 is used as a HEALTHY
output, this pin needs to be attached to GND or VBATT via a
resistor.
The COMP1_CH1 (Channel 1 primary Compensation) pin is the
primary compensation input of the channel 1 step-down buck
controller. The COMP1_CH1 pin is internally connected to a
programmable resistor divider.
The COMP2_CH1 (Channel 1 secondary Compensation) pin is
the secondary compensation input of the channel 1 step-down
buck controller.
2111 2.4 6/24/2008
1
OUT
HSDRV_CH0
2
OUT
HEALTHY
(nRESET)
3
IN
COMP1_CH0
4
5
6
7
8
9
IN
IN
I/O
IN
OUT
PWR
COMP2_CH0
VM_CH0
SDA
SCL
LSDRV_CH1
HVSUP1
10
OUT
HSDRV_CH1
11
IN
HOST_RESET
12
IN
COMP1_CH1
13
IN
COMP2_CH1
Summit Microelectronics, Inc
5
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