SMB214A/B/C
High-power, Three-channel Programmable DC-DC System Power Managers
FEATURES & APPLICATIONS
•
Digital programming of all major parameters via
I
2
C interface and non-volatile memory
•
Output voltage set point
•
Input/battery voltage monitoring
•
Output power-up/down sequencing
•
Dynamic voltage control of all outputs
•
UV/OV monitoring of all outputs
•
Enable/Disable outputs independently
•
User friendly Graphical User Interface (GUI)
•
Three synchronous step-down output channels
•
Integrated RESET monitor
•
+2.7V to +6.0V Input Range
•
Highly accurate output voltage: <2.5%
•
Factory programmable dead times
•
0% to 100% Duty Cycle operation
•
Undervoltage Lockout (UVLO) with hysteresis
•
Operating frequency: 400kHz (SMB214A), 800kHz
(SMB214B), 1MHz (SMB214C)
Preliminary Information
INTRODUCTION
The SMB214A/B/C are highly integrated and flexible three-
channel power managers designed for use in a wide range of
applications. The built-in digital programmability allows system
designers to custom tailor the device to suit almost any multi-
channel power supply application from digital camcorders to
set-top boxes. Complete with a user friendly GUI, all
programmable settings, including output voltages and
input/output voltage monitoring, can be customized with ease.
The SMB214A/B/C integrate all the essential blocks required to
implement a complete three-channel power subsystem
consisting of three synchronous step-down “buck” controllers.
Additionally sophisticated power control/monitoring functions
required by complex systems are built-in. These include
digitally programmable output voltage set point, power-
up/down sequencing, enable/disable, dynamic voltage
management and UV/OV monitoring on all channels.
The integration of features and built-in flexibility of the
SMB214A/B/C allows the system designer to create a “platform
solution” that can be easily modified via software without major
hardware changes. Combined with the re-programmability of
the SMB214A/B/C, this facilitates rapid design cycles and
proliferation from a base design to future product generations.
The SMB214A/B/C are suited to a wide variety of applications
with an input range of +2.7V to +6.0V. Higher input voltage
operation can easily be implemented with a small number of
external components. Output voltages are extremely accurate
(<2.5%). Communication is accomplished via the industry
standard I
2
C bus. All user-programmed settings are stored in
non-volatile EEPROM. The devices are offered in both the
commercial and the industrial operating temperature range.
The package type is a lead-free, RoHS compliant, 5x5 QFN-
32.
Applications
•
•
•
•
•
•
Car & Marine Navigation Systems
Set-top Boxes
TVs
DDR Memory
Mobile Computing/PDAs
Office Equipment
•
DMB Systems
SIMPLIFIED APPLICATIONS DRAWING
+2.7V to +6.0V
or
Li-Ion
SMB214
I2C/SMBus
Enable Input
System
Control
and
Monitoring
+0.5V to Vin (Prog.) @ 5A
CPU Core
3 Step-
Down
(Buck)
Channels
+0.5V to Vin (Prog.) @ 5A
Memory, I/O
RESET Output
(Power Good)
RESET
Monitor
+0.5V to Vin (Prog.) @ 5A
Analog/RF
Figure 1 – Applications schematic featuring the SMB214A/B/C programmable DC-DC controllers.
Note: This is an applications example only. Some pins, components and values are not shown.
© SUMMIT
Microelectronics, Inc. 2007
757 N. Mary Avenue • Sunnyvale CA 94085
Phone 408 523-1000 • FAX 408 523-1266
http://www.summitmicro.com/
2128 2.0 6/20/2008
1
SMB214A/B/C
Preliminary Information
GENERAL DESCRIPTION
The SMB214A/B/C are fully programmable DC-DC
controllers that incorporate power delivery and
advanced power monitoring and control functionality.
The devices integrate three synchronous “buck” step-
down controllers in a space saving 5x5 QFN-32
package.
The SMB214A uses a fixed 400kHz whereas the
SMB214B uses a fixed 800kHz, and the SMB214C a
fixed 1MHz Pulse Width Modulation (PWM) control
circuit.
A type-three voltage mode compensation
network is used offering a cost effective solution without
compromising transient response performance. By
utilizing external N- and P–type MOSFET transistors
the efficiency and load current level can be customized
to fit a wide array of system requirements.
The SMB214A/B/C contain three buck outputs capable
of producing an output voltage less than the input
voltage. Each buck output voltage is set by an internal
resistor divider and a programmable voltage reference.
The integrated resistor divider eliminates the cost and
space necessary for external components and has
several programmable values.
Through the
programmability of the reference and the resistor
divider, practically any output voltage smaller than the
battery can be produced without the need to change
external components.
The SMB214A/B/C are capable of power-on/off
cascade sequencing where each channel can be
assigned one of three unique sequence positions.
During sequencing each channel in a given sequencing
position is guaranteed to reach its programmed output
voltage before the channel(s) occupying the next
sequence position initiate their respective soft-start
sequence.
A unique programmable delay exists
between each power on/off sequence position. In
addition to power on/off sequencing all supplies can be
2
powered on/off individually through an I C command or
by assertion of the enable pin.
Each output voltage is monitored for under-voltage and
over-voltage (UV/OV) conditions, using a comparator-
based circuit where the output voltage is compared
against an internal programmable reference.
An
additional feature of the output voltage monitoring is a
programmable glitch filter capable of digitally filtering a
transient OV/UV fault condition from a true system
error. When a fault is detected for a period in excess of
the glitch filter, all supplies may be sequenced down or
immediately disabled and an output status pin can be
asserted.
The current system status is always
accessible via internal registers containing the status of
all three channels.
The SMB214A/B/C also possess an Under-voltage
Lockout (UVLO) circuit to ensure the devices will not
power up until the input voltage has reached a safe
operating voltage.
The UVLO function exhibits
hysteresis, ensuring that noise or a brown out voltage
on the supply rail does not inadvertently lead to a
system failure.
The
SMB214A/B/C
provide
dynamic
voltage
management over all of their output voltages. Through
2
an I C command, all output voltage levels can be
increased or decreased to a pre-programmed level. In
addition, each output is slew rate limited by soft-start
circuitry that requires no external capacitors.
All programmable settings on the SMB214A/B/C are
stored in non-volatile registers and are easily accessed
and modified over an industry standard I
2
C serial bus.
For fastest prototype development times Summit offers
an evaluation card and a Graphical User Interface
(GUI).
Summit Microelectronics, Inc.
2128 2.0 6/20/2008
2
SMB214A/B/C
TYPICAL APPLICATION
VIN: +2.7V to +6.0V
SMB214A/B/C
VBATT
VDDCAP
GND
HSDRV_CH2
+0.8V to VIN @ 5A
HVSUP2
LSDRV_CH2
SDA
SCL
PWREN
HOST_
RESET
HEALTHY/
nRESET
VM_CH2
COMP1_CH2
COMP2_CH2
HVSUP1
HSDRV_CH1
HVSUP0
HSDRV_CH0
+0.8V to VIN @ 5A
LSDRV_CH1
+0.8V to VIN @ 5A
LSDRV_CH0
VM_CH1
COMP1_CH1
VM_CH0
COMP1_CH0
COMP2_CH0
COMP2_CH1
Figure 2 – Typical application schematic
Summit Microelectronics, Inc
2128 2.0 6/20/2008
3
SMB214A/B/C
INTERNAL BLOCK DIAGRAM
COMP2_CH[0,1,2]
VM_CH[0,1,2]
100k
–
+
OA
+
–
CLAMP
MAX LIMIT
LOW LIMIT
DUTY
CYCLE
LIMIT
OSC
Fixed 400/800/
1000kHz
Channel 0,1,2
Synchronous
buck
PWM Converter
HVSUP[0,1,2]
HSDRV[0,1,2]
I
2
C/SMBUS
SDA
SCL
COMP1_CH[0,1,2]
VREF
LEVEL
SHIFTER
DIGITAL TO
VDDCAP
ANALOG
CONVERTER
VREF
DEADTIME
+
–
GLITCH
FILTER
OVER VOLTAGE
DETECTION
LSDRV[0,1,2]
SEQUENCING
AND
MONITORING
LOGIC
ENABLE
PWREN
+
–
GLITCH
FILTER
UNDER VOLTAGE
DETECTION
VBATT
GND
BANDGAP
VREF
VDD_CAP
2.5V
REGULATOR
+
–
UV2
D
Q
LEVEL
SHIFTER
VREF
+
–
UV1
Figure 3 –SMB214A/B/C internal block diagram. Programmable functional blocks include: level shifters, digital
to analog converter and the VM_CH[0,1,2] voltage dividers.
Summit Microelectronics, Inc
2128 2.0 6/20/2008
4
SMB214A/B/C
PIN DESCRIPTION
Pin Number
Pin Type
Pin Name
Pin Description
The HSDRV_CH0 (Channel 0 High-side Driver) pin is the upper
switching node of the channel 0 synchronous step-down buck
controller. Attach to the gate of p-channel MOSFET. A delay
exists between the assertion of HSDRV_CH0 and assertion of
LSDRV_CH0 to prevent excessive current flow during switching.
The HEALTHY pin is an open drain output. High when all
enabled output supplies are within the programmed levels.
HEALTHY will ignore any disabled supply.
There is a
programmable glitch filter on the under-voltage and over-voltage
sensors so that short transients outside of the limits will be
ignored by HEALTHY. This pin can also be programmed to act
as a Reset Output (nRESET). In this case, it releases with a
programmable delay after all outputs are valid. When used, this
pin should be pulled high by an external pull-up resistor.
The COMP1_CH0 (Channel 0 primary Compensation) pin is the
primary feedback input of the channel 0 step-down buck
controller. The COMP1_CH0 pin is internally connected to a
programmable resistor divider.
The COMP2_CH0 (Channel 0 secondary Compensation) pin is
the secondary feedback input of the channel 0 step-down buck
controller.
The VM_CH0 (Channel 0 Voltage Monitor) pin connects the
channel 0 step-down controller output. Internally the VM_CH0 pin
connects to a programmable resistor divider.
SDA (Serial Data) is an open drain bi-directional pin used as the
I
2
C data line. SDA must be tied high through a pull-up resistor.
SCL (Serial Clock) is an open drain input pin used as the I
2
C
clock line. SCL must be tied high through a pull-up resistor.
The LSDRV_CH1 (Channel 1 Low-side Driver) pin is the lower
switching node of the channel 1 synchronous step-down buck
controller. Attach to the gate of n-channel MOSFET.
Channel 1 High Voltage Supply for Channel 1 buck driver.
The HSDRV_CH1 (Channel 1 High-side Driver) pin is the upper
switching node of the channel 1 synchronous step-down buck
controller. Attach to the gate of p-channel MOSFET. A delay
exists between the assertion of HSDRV_CH1 and assertion of
LSDRV_CH1 to prevent excessive current flow during switching.
The HOST_RESET pin is an active high reset input. When this
pin is asserted high, the nRESET output will immediately go low.
When HOST_RESET is brought low, nRESET will go high after a
programmed reset delay. When pin 2 is used as a HEALTHY
output, this pin needs to be attached to GND or VBATT via a
resistor.
The COMP1_CH1 (Channel 1 primary Compensation) pin is the
primary compensation input of the channel 1 step-down buck
controller. The COMP1_CH1 pin is internally connected to a
programmable resistor divider.
The COMP2_CH1 (Channel 1 secondary Compensation) pin is
the secondary compensation input of the channel 1 step-down
buck controller.
2128 2.0 6/20/2008
1
OUT
HSDRV_CH0
2
OUT
HEALTHY
(nRESET)
3
IN
COMP1_CH0
4
5
6
7
8
9
IN
IN
I/O
IN
OUT
PWR
COMP2_CH0
VM_CH0
SDA
SCL
LSDRV_CH1
HVSUP1
10
OUT
HSDRV_CH1
11
IN
HOST_RESET
12
IN
COMP1_CH1
13
IN
COMP2_CH1
Summit Microelectronics, Inc
5
FPGA/CPLD
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