SMT4504
Four-Channel Loss-Less Trakker
TM
Power Supply Manager
FEATURES & APPLICATIONS
•
Loss-Less Tracking function
-
No power MOSFET switches
•
Programmable Slew-Rate, Tracking and Voltage
Monitoring Functions
•
Directly Interfaces to DC-DC Converters,
Monolithic Controllers or LDOs
•
Programmable Sequence Orders
•
Programmable Tracking Slew Rates
•
Eliminates Series Power MOSFETs
•
Programmable OV/UV Threshold Limits
•
Under Voltage Lock-Out (VDD and VCTRL_SUP)
•
4k-Bit user configurable Nonvolatile Memory
•
I
2
C 2-wire serial bus for programming
configuration and monitoring status
Preliminary Information
1
(See Last Page)
INTRODUCTION
The SMT4504 is an intelligent power supply
sequencer, tracker, and voltage monitor. The
SMT4504 tracks or sequences up to 4 power supplies
by uniquely controlling the Enable and TRIM (Soft-
Start) functions of DC-DC converters, Monolithic
Controllers or LDOs. Each Channel is individually
programmable for undervoltage/overvoltage threshold
settings, sequence position and slew rates. Two or
more supplies allocated to the same sequence
position are tracked, while assigning individual
supplies to a unique sequence position causes them
to be sequenced with controlled slew rates.
The SMT4504 monitors the supplies for faults and
is programmable to take any of several actions upon
the occurrence of a fault. The voltage monitoring
threshold step size is better than
±1%.
Power supply sequencing can be executed in any
order. During power-off sequencing, the SMT4504
sequences the supplies in the reverse order as power-
on.
Using the I
2
C interface, a host system can
communicate with the SMT4504 status register,
optionally control power-on/off software and utilize 4K-
bits of nonvolatile memory.
Applications
•
Monitor, Sequence and Slew-Rate Control of
Distributed Power and Point of Use Power
Supplies
•
Multi-voltage Processors, DSPs, ASICs used in
Telecom, CompactPCI or server systems
SIMPLIFIED APPLICATIONS DRAWING
5V
12V
VCTRL_SUP
GND
VDD
5V
DC-DC
Converter
VIN
V+
TRIM
ON/OFF
V-
2.5VIN
GND
DSP/
µP/
NPU/
FPGA/
ASIC
VDD_CAP
VCTRL
A
PUP
A
I2C
BUS
SDA
SCL
SMT4504
VM
A
Monolithic
Controller
VIN
VCTRL
B
PWR_ON
PWR_ON#
PUP
B
-E/A
Soft-Start
V+
V-
1.2VIN
GND
IRQ#
VM
B
IRQ#
Figure 1 – Applications Schematic, the SMT4504 Loss-Less Trakker
TM
can track different types of supplies
together.
Note: This is an applications example only. Some pins, components and values are not shown.
Summit Microelectronics, Inc
2071 1.1 01/07/05
1
SMT4504
Preliminary Information
3 .3 V
2 .5 V
1 .8 V
1 .5 V
Figure 2A – Example Power Supply Sequencing and Tracking using the SMT4504. Any order of supply
sequencing/tracking can be applied using the SMT4504.
GENERAL DESCRIPTION
The SMT4504 consists of several major functional
blocks: the power supply monitors, the sequencing and
tracking outputs; the programmable output circuitry; the
timing and control block; the I
2
C interface and the
nonvolatile memory array.
The analog acquisition system monitors all channels via
the OV/UV sensors. The UV/OV sensors are the four
power supply voltage channels and the VDD and
VCTRL_SUP supplies. The setting of the OV/UV trip
points is made via the I
2
C serial data port.
Once PWR_ON is asserted a programmable delay timer
must first expire after which the PUP (Point of Use
Power) output(s) so required are enabled. The PUPs are
generally connected to the Enable pin of the converter
controlled by the SMT4504 Any channel not requiring
closed-loop tracking of the voltage is programmed to
assert its output (PUP) once the previous sequence
timer has expired. Otherwise all PUPs are asserted
upon the completion of the PWR_ON delay timer.
The power supply manager block is also used to assign
a given power supply a sequence position; sequence
timeout period and track-up/down slew rate setting.
These settings determine the time and the rate at which
each supply is turned on. When more than one supply is
assigned to a sequence position their voltages will be
tracked during the period of time when they are turned
on via the VCTRL
X
pins and monitored via the VM
X
pins.
These events are controlled by the sequence and
tracking block.
An additional feature of the SMT4504 allows the
supplies that are assigned the same sequence position
to be tracked at the same or different slew rates for
applications requiring supplies to be started at the same
time but to ramp up at different rates. (Figure 2A)
The next major block is a programmable output block.
The SMT4504 provides a great deal of flexibility in
choosing the fault trigger source for the fault outputs.
The sources include multiple combinations of UV/OV
conditions. The fault outputs’ assertion polarities are
also programmable.
Programming of the SMT4504 is performed over the
industry standard I
2
C, 2-wire serial data interface. It
allows configuration of the device, real-time control of
the power-on/power-off processes and reading of the
status registers. The bus interfaces the host to 4k bits of
nonvolatile memory and the programmable configuration
registers.
The 4k bits of user configurable nonvolatile memory
uses industry standard non-volatile memory technology.
Summit Microelectronics, Inc
2071 1.1 01/07/05
2
SMT4504
Advanced Information
3.3V
2.5V
1.8V
1.5V
t
SR
= 125% of Setting
t
SR
= 150% of Setting
t
SR
= 75% of Setting
t
SR
= 100% of Setting
Figure 2B – Example Power Supply Tracking flexibility using the SMT4xx4 set to the same sequence
position but different slew rates on each channel.
Summit Microelectronics, Inc
2071 1.1 01/07/05
3
SMT4504
Preliminary Information
SIMPLIFIED BLOCK DIAGRAM
HEALTHY
VM
A
Supply Manager A
Force
Shutdown
Arbitration
VM
B
Supply Manager B
MR#
IRQ & RST
Logic
IRQ_CLR#
IRQ#
RST#
VCTRL
A
PUP
A
VCTRL
B
PUP
B
VCTRL
C
VM
C
VCTRLTracking/
Sequence Logic
PUP
C
VCTRL
D
PUP
D
LINK_A
VM
D
Supply Manager D
Enable
Logic
LINK_B
VRLINK
Supply Manager C
A0
FS#
PWR_ON
WP
VDD/VGG
Control
Bus Interface
Configuration,
Status and GP
Registers
A1
SCL
SDA
VDD_CAP
GND
VGG
VDD
Summit Microelectronics, Inc
2071 1.1 01/07/05
4
SMT4504
Preliminary Information
PIN DESCRIPTIONS
Pin Name
VCTRL
C
VM
C
VCTRL
D
VM
D
IRQ
HEALTHY
RST
Type
OUT
IN
OUT
IN
OUT
OUT
OUT
Number
1
2
3
4
5
6
7
Function
Control voltage used to track/sequence the converters
Channel C converter output or sense+ line
Control voltage used to track/sequence the converters
Channel D converter output or sense+ line
Programmable active high/low open drain latched output. Asserted when
programmed power supply is in a fault condition.
Programmable active high/low output asserted when all Fault conditions are
clear
Programmable active high/low open drain output signals when all
programmed power supplies are within the monitored limits and the MR signal
is inactive. RST has a programmable timeout period with options for
0.64/50/100/200ms.
Active low open drain I/O connected to LINK_B pin other SMT4504’s for
linked operation
Active low open drain I/O connected to LINK_A pin other SMT4504’s for
linked operation
Ground of the part
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low input internally pulled up to VDD_CAP with 75k ohm resistor
Force shutdown active low I/O used to turn off all converter enable signals.
Do not drive FS# high.
Active high I/O signals the start of the power sequencing. When asserted the
part will sequence the supplies on and when de-asserted the part will
sequence the supplies off. Do not drive PWR_ON high.
External tracking ramp reference
Bi-directional I
2
C Data line
I
2
C Clock line
I
2
C device bus address assignment pin.
I
2
C device bus address assignment pin.
I
2
C device bus address assignment pin.
Programmable active high/low write protect input. When asserted the
configuration registers are write protected and the write protect volatile
register is set.
Active low input. When asserted the RST output will be allowed to de-assert
after a reset timeout if there are no reset sources still active.
Ground of the part
Power supply of the part
LINK_B
LINK_A
GND
STATUS
A
STATUS
B
STATUS
C
STATUS
D
SEATED#
FS#
PWR_ON
VRLINK
SDA
SCL
A0
A1
A2
WP
MR#
GND
VDD
I/O
I/O
PWR
OUT
OUT
OUT
OUT
IN
I/O
I/O
I/O
DATA
CLK
IN
IN
IN
IN
IN
PWR
PWR
8
9
10
11
12
13
14
15
16
17
18
25
26
27
28
29
30
31
34
35
Summit Microelectronics, Inc
2071 1.1 01/07/05
5
FPGA/CPLD
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