SUMMIT
MICROELECTRONICS, Inc.
SMS2902/SMS2904/SMS2916
Voltage Supervisory Circuit With Watchdog Timer
FEATURES
• Precision Voltage Monitor
– V
CC
Supply Monitor
- Complementary reset outputs for complex
microcontroller systems
- Integrated memory write lockout function
- No external components required
•Watchdog Timer
– 1600 ms, internal
• Two Wire Serial Interface (I
2
C™)
• Extended Programmable Functions
available on SMS24
• High Reliability
– Endurance: 100,000 erase/write cycles
– Data retention: 100 years
• 8-Pin SOIC Packages
OVERVIEW
The SMS29xx is a power supervisory circuit that monitors
V
CC
and will generate complementary reset outputs. The
reset pins also act as I/Os and may be used for signal
conditioning. The SMS29xx also has an on-board watch-
dog timer.
The SMS29xx integrates a nonvolatile serial memory. It
features the industry standard I
2
C serial
interface allowing quick implementation in an end-users’
system.
BLOCK DIAGRAM
VCC
8
SCL
SDA
6
5
NONVOLATILE
MEMORY
ARRAY
WRITE
CONTROL
PROGRAMMABLE
RESET PULSE
GENERATOR
2
RESET#
+
–
VTRIP
RESET
CONTROL
7
WDI#
1
1.26V
WATCHDOG
TIMER
RESET
4
GND
2028 T BD 2.0
SUMMIT MICROELECTRONICS, Inc.
•
300 Orchard City Drive, Suite 131
•
Campbell, CA 95008
•
Telephone 408-378-6461
•
Fax 408-378-6586
•
www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000
2028 5.1 8/2/00
Characteristics subject to change without notice
1
SMS2902/SMS2904/SMS2916
PIN CONFIGURATIONS
PIN NAMES
Symbol
WDI#
Pin
1
Description
Watchdog Input /a high to
low transition will clear the
watchdog timer
Active Low RESET Input/Output
No Connect, tie to ground
or leave open
Analog and Digital Ground
Serial Memory Input/
Output data line
Serial Memory clock input
Active High RESET Input/
Output
Supply Voltage
2028 PGM T1.1
8-Pin SOIC
WDI#
RESET#
NC
GND
1
2
3
4
8
7
6
5
VCC
RESET
SCL
SDA
RESET#
NC
GND
SDA
SCL
RESET
V
CC
2
3
4
5
6
7
8
2028 T PCon 2.0
CAPACITANCE
T
A
= 25°C, f = 100KHz
Symbol
C
IN
L
OUT
Parameter
Input Capacitance
Output Capacitance
Max
5
8
Units
pF
pF
2028 PGM T2..0
t
R
t
F
t
H IGH
t
LOW
t
SU:STO
SCL
t
SU:SDA
t
HD:SDA
t
HD:DAT
t
SU:DAT
t
BUF
SDA In
t
DH
t
AA
SDA Out
2028 ILL5.0
FIGURE 1. SERIAL BUS TIMING DIAGRAM
2028 5.1 8/2/00
2
SMS2902/SMS2904/SMS2916
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias
............................................................................................................................... -40°C to +85°C
Storage Temperature
..................................................................................................................................... -65°C to +125°C
Soldering Temperature (less than 10 seconds) ................................................................................................................... 300°C
Supply Voltage ............................................................................................................................................................. 0 to 6.5V
Voltage on Any Pin ....................................................................................................................................... -0.3V to V
CC
+0.3V
ESD Voltage (JEDEC method) .......................................................................................................................................... 2,000V
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses
beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min
0°C
-40°C
Max
+70°C
+85°C
2028 PGM T3.0
DC ELECTRICAL CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL
Parameter
Supply Current (CMOS)
Standby Current (CMOS)
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Conditions
SCL = CMOS Levels @ 100KHz
SDA = Open
All other inputs = GND or V
CC
SCL = SDA = V
CC
All other inputs = GND
V
IN
= 0 To V
CC
V
OUT
= 0 To V
CC
S0, S1, S2, SCL, SDA, RESET#
S0, S1, S2, SCL, SDA, RESET
I
OL
= 3mA SDA
0.7xV
CC
0.4
V
CC
=5.5V
V
CC
=3.3V
V
CC
=5.5V
V
CC
=3.3V
Min
Max
3
2
50
25
10
10
0.3xV
CC
Units
mA
mA
µA
µA
µA
µA
V
V
V
2028 PGM T4.0
AC ELECTRICAL CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)
Symbol
Parameter
SCL Clock Frequency
Clock Low Period
Clock High Period
Bus Free Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
Clock to Output
Data Out Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
Noise Spike Width
@ SCL, SDA Inputs
Write Cycle Time
Noise Suppression Time Constant
SCL Low to SDA Data Out Valid
SCL Low to SDA Data Out Change
Before New Transmission
Conditions
2.7V to 4.5V
Min
0
4.7
4.0
4.7
4.7
4.0
4.7
0.3
0.3
1000
300
250
0
100
10
3.5
Max
100
4.5V to 5.5V
Min
Max
400
1.3
0.6
1.3
0.6
0.6
0.6
0.2
0.2
300
300
100
0
100
10
0.9
Units
KHz
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ms
2028 PGM T5.0
f
SCL
t
LOW
t
HIGH
t
BUF
t
SU:STA
t
HD:STA
t
SU:STO
t
AA
t
DH
t
R
t
F
t
SU:DAT
t
HD:DAT
T
I
t
WR
2028 5.1 8/2/00
3
SMS2902/SMS2904/SMS2916
tGLITCH
VTRIP
VRVALID
tRPD
tPURST
tPURST
VCC
RESET#
tRPD
RESET
2028 T fig02 2.0
FIGURE 2. RESET OUTPUT TIMING
RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS
TA=-40°C to +85°C
Symbol
V
TRIP
Parameter
Reset Trip Point
Part no.
Suffix
A (or) Blank
B
2.7
Min.
4.250
4.50
2.55
Typ.
4.375
4.625
2.65
200
Max.
4.5
4.75
2.75
5
1
30
0.4
V
CC
-.75
1.20
1.20
1.20
1.20
1.25
1.25
1.25
1.25
1.30
1.30
1.30
1.30
5
5
1600
Unit
V
V
V
ms
µs
V
ns
V
V
V
V
V
V
µs
µs
ms
t
PURST
t
RPD
V
RVALID
t
GLITCH
V
OLRS
V
OHRS
V
ULH
V
UHL
V
OLH
V
OHL
t
VD1
t
VD2
t
WDTO
Reset Timeout
V
TRIP
to RESET Output Delay
RESET Output Valid to V
CC
min. Guarantee
Glitch Reject Pulse Width note 1
RESET Output Low Voltage I
OL
= 1mA
RESET High Voltage Output I
OH
= 800µA
V
SENSE
Under-voltage threshold low to high
V
SENSE
Under-voltage threshold high to low
V
SENSE
Over-voltage threshold low to high
V
SENSE
Over-voltage threshold high to low
Delay to V
LOW
Active
Delay to V
LOW
Released
Watchdog timeout Period
2028 5.1 8/2/00
4
SMS2902/SMS2904/SMS2916
WDI#
< t
WDTO
t
WDTO
t
PURST
RESET#
WDI#
t
WDTO
t
PURST
t
WDTO
t
PURST
RESET#
2028 T fig03 2.0
FIGURE 3. WATCHDOG TIMER TIMING DIAGRAM
RESET# (in)
RESET# (out)
t
PURST
t
PURST
RESET (out)
2028 T fig04 2.0
FIGURE 4.
RESET
AS AN INPUT FUNCTION
2028 5.1 8/2/00
5
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