SUMMIT
MICROELECTRONICS, Inc.
SMS1242
2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset
Microprocessor Supervisory Circuits
FEATURES
• Supply voltage monitor
- Nominal V
RST
of 2.45V, 2.65V, 2.95V, 4.45V,
4.55V or 4.65V
- RESET# Outputs Guaranteed true at V
CC
= 1V
- 150ms Reset Delay Time
• Second voltage monitor
- V
SENSE
Input
- 1.25V threshold ±1%
• Manual Reset Input
• Includes 16k-bits nonvolatile memory
- Industry standard 2-wire serial interface
OVERVIEW
The SMS1242 microprocessor supervisory circuit re-
duces the complexity and number of components required
to monitor the supply voltage in +5V, +3V and +2.5V
systems. The SMS1242 will significantly improve system
reliability and accuracy when compared to implementing
the same functions with discrete components.
The SMS1242 provides reset output during power-up,
power-down, and brown-out conditions. It has a 1.25V
threshold input detector for power-fail warning, low battery
detection, or monitoring a secondary power supply. The
part also integrates a separate active low manual reset
input.
It also has 16k-bits of nonvolatile memory accessible over
an industry standard 2-wire serial interface.
FUNCTIONAL BLOCK DIAGRAM
VCC
8
SCL
SDA
6
5
NONVOLATILE
MEMORY
ARRAY
VSENSE 3
+
–
7 MR#
2 RESET1#
+
–
VTRIP
RESET
GENERATOR
1
RESET2#
1.25V
4
GND
2038 BD 2.0
© SUMMIT MICROELECTRONICS, Inc. 2000 • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Phone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
2038 2.0 6/8/00
Characteristics subject to change without notice
1
SMS1242
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
–55°C to 125°C
Storage Temperature
–65°C to 150°C
Terminal Voltage (With Respect to Ground)–0.3V to 6V
Lead Solder Temperature (10 secs)
300°C
*COMMENT
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or
any other conditions outside those listed in the operation sec-
tions of this specification is not implied. Exposure to any abso-
lute maximum rating for extended periods may affect device
performance and reliability.
Symbol
V
CC
I
CC
Parameter
Operating supply voltage
Conditions
Min.
1
Typ.
Max.
5.5
Units
V
µA
µA
mA
V
V
V
V
V
V
mV
3.6V < V
CC
< 5.5V
Supply current
3.6V > V
CC
Memory access (SMS1243 only)
Device option A
Device option B
V
RST
Reset threshold
Device option C
Device option D
Device option E
Device option F
V
HYST
t
RST
V
OL
I
MR
t
MR
V
IL
V
IH
V
SNS
V
CC
V
RST
Hysterisis
Reset pulse width
RESET1# output low voltage
MR# pullup current
MR# pulse width
MR# input threshold
MR# input threshold
V
SENSE
input threshold
RESET2# output low voltage
V
CC
= V
RST
min., V
SENSE
falling
I
SINK
= 1.2mA, V
CC
= V
RST
min.
I
SINK
= 200µA, V
CC
= 1.2V
0.7
×
V
CC
1.20
50
I
SINK
= 1.2mA, V
CC
= V
RST
min.
I
SINK
= 200µA, V
CC
= 1.2V
100
4.375
4.625
4.425
2.425
2.625
2.925
25
25
50
50
3
4.425
4.675
4.475
2.450
2.650
2.950
50
150
4.475
4.725
4.525
2.475
2.675
2.975
200
0.3
0.3
ms
V
V
µA
ns
100
0.6
V
V
1.25
1.30
0.3
0.4
V
V
V
2038 Elect Table 2.0
SUMMIT MICROELECTRONICS, Inc.
2038 2.0 6/8/00
2
SMS1242
PIN NAMES
Pin
Signal
Function
PIN CONFIGURATION
8-Pin SOIC
1
Active low output with weak pullup.
Driven low by: V
SENSE
below thresh-
old; or V
CC
below threshold while
RESET1#
MR# is below threshold. Remains
low for 150ms after V
SENSE
, or V
CC
and MR#, is above threshold.
RESET2#
V
SENSE
GND
Same as Reset1#, except open
drain connection
Threshold detector input for the
Resets
Ground
RESET1#
RESET2#
V
SENSE
GND
1
2
3
4
8
7
6
5
V
CC
MR#
SCL
SDA
2
3
4
5
6
7
8
2038 T PCon 2.0
SDA/GND SMS1243 Data I/O, or ground
SCL/GND SMS1243 Data Clock, or ground
MR#
V
CC
Manual input for Resets
Supply voltage
2038 Pin Table 2.0
V
CC
V
RST
V
RST
t
RST
RESET#
MR#
V
IL
t
MR
V
IH
t
RST
t
RST
V
SENSE
Figure 1. Reset Waveforms
V
SNS
2038 T Fig01 2.0
2038 2.0 6/8/00
SUMMIT MICROELECTRONICS, Inc.
3
SMS1242
4.5
4.4
GLITCH AMPLITUDE (V)
4.3
4.2
4.1
4.0
3.9
3.8
0
1
2
3
4
5
6
7
8
9
10
2038 Fig02 2.0
PULSE WIDTH (ms)
Figure 2. Supply Voltage Noise Rejection, V
RST
=4.55V, T
A
= 25ºC
V
RST
V
CC
2V
1.25V
0V
V
SE
NS
E
0V
V
CC
0V
RESET#
0V
RESET#
500ms/Div.
Figure 3. RESET Output vs. Supply
Figure 4. RESET Output vs. V
SENSE
SUMMIT MICROELECTRONICS, Inc.
2038 2.0 6/8/00
4
SMS1242
DEVICE OPERATION
The SMS1242 provides a precision reset function for a
microcontroller or microprocessor during power-up,
power-down and brown-out conditions. The device will
monitor two independent voltage supplies and will gener-
ate a reset condition when either supply is invalid. It is
configured with two outputs, both driven by the same
conditions. They are open drain and will track each other
but the outputs are not internally tied together.
Because RESET1# and RESET2# are essentially open
drain outputs (RESET1# has a weak internal pullup,
RESET2# does not) they can be independently driven low
by external signals. This can be very useful in a dual
processor system or in a combined processor/ASIC sys-
tem where, either for system operation or system test, the
processors or ASICs must be independently held in reset
without resetting the other portion of the system.
SUPPLY MONITOR
(Assume V
SENSE
> V
SNS
) During power-up the SMS1242
monitors the supply voltage. The RESET1# and RE-
SET2# outputs are guaranteed to be driven low once V
CC
reaches 1V. As V
CC
rises RESET1# and RESET2#
remain asserted until V
CC
reaches the V
RST
threshold. As
V
CC
passes through V
RST
an internal timer is started to
continue driving the outputs for an additional 150ms
(nominal).
If a power-fail or brown-out condition occurs (V
CC
< V
RST
)
RESET1# and RESET2# will be asserted. They will
remain active so long as V
CC
is below V
RST
. Because the
internal timer will be continuously reset so long as V
CC
is
below V
RST
, a brownout condition that interrupts a previ-
ously initiated reset pulse causes an additional reset delay
from the time the V
CC
passes back through V
RST
.
During power down conditions, once V
CC
drops below
V
RST
, RESET1# and RESET2# are guaranteed to be
asserted for V
CC
≥
1V.
V
SENSE
MONITOR
(Assume V
CC
is >V
RST
) The SMS1242 continuously
monitors the VSENSE input. The RESET1# and RE-
SET2# outputs will be driven low so long as V
SENSE
is <
VSNS. As V
SENSE
passes through V
SNS
an internal timer
is started to continue driving the outputs for an additional
150ms (nom.).
If a power-fail condition occurs (V
SENSE
falls below V
SNS
)
RESET1# and RESET2# will be asserted. They will re-
main active so long as V
SENSE
is below V
SNS
. Because
the internal timer will be continuously reset so long as
V
SENSE
is below V
SNS
, a brownout condition that inter-
rupts a previously initiated reset pulse causes an addi-
tional reset delay from the time V
SENSE
becomes greater
than V
SNS
.
MANUAL RESET
The manual reset input allows RESET1# and RESET2# to
be activated by a pushbutton switch. The switch is
effectively debounced by the 100ms minimum t
RST
(RE-
SET pulse width). MR# can also be driven by an external
logic input that meets the 50ns minimum pulse width
required.
Unregulated
+12V DC
DC to DC
Converter
3.3V Out
3.3V
MCU
VCC
VSENSE
MCU #1
RESET1#
MR#
VCC
RESET1#
SMS1242
SMS1242
Test Point #1
MR#
RESET2#
ASIC or MCU #2
1.8V
RESET2#
VSENSE
Low Voltage
High Speed
ASIC
Test Point #2
2038 ILL7.0
2038 ILL8.0
Figure 5. Typical Multi-MCU Implementation
2038 2.0 6/8/00
Figure 6. Typical Dual Voltage Implementation
5
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