Tri path Technol og y, I nc. - Techni cal I nformation
TA2024C
STEREO 15W (4Ω) CLASS-T™ DIGITAL AUDIO AMPLIFIER USING
DIGITAL POWER PROCESSING™ TECHNOLOGY
Preliminary Information
Revision 1.0 – January 2006
GENERAL DESCRIPTION
The TA2024C is a 15W/ch continuous average two-channel Class-T Digital Audio Power Amplifier IC
using Tripath’s proprietary Digital Power Processing™ technology. Class-T amplifiers offer both the
audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
The TA2024C has incorporated specific changes to improve the click and pop performance over
previous devices such as TA2024 and TA2024B. The TA2024C is recommended for all new designs
that previously used the TA2024 or TA2024B.
APPLICATIONS
FEATURES
Computer/PC Multimedia
DVD Players
Cable Set-Top Products
Televisions
Video CD Players
Battery Powered Systems
BENEFITS
Fully integrated solution with FETs
Easier to design-in than Class-D
Reduced system cost with no heat sink
Dramatically improves efficiency versus Class-
AB
Signal fidelity equal to high quality linear
amplifiers
High dynamic range compatible with digital
media such as CD, DVD, and Internet audio
TYPICAL PERFORMANCE
Class-T architecture
Single Supply Operation
“Audiophile” Quality Sound
0.03% THD+N @ 9W, 4Ω
0.10% IHF-IM @ 1W, 4Ω
11W @ 4Ω, 0.1% THD+N
6W @ 8Ω, 0.1% THD+N
High Power
15W @ 4Ω, 10% THD+N
10W @ 8Ω, 10% THD+N
High Efficiency
81% @ 15W, 4Ω
90% @ 10W, 8Ω
Dynamic Range = 98 dB
Mute and Sleep inputs
Enhanced Turn-on & turn-off pop
suppression
Over-current protection
Over-temperature protection
Bridged outputs
36-pin Power SOP package
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TA2024C –KL/1.0/01.06
Tri path Technol og y, I nc. - Techni cal I nformation
A B S O L U T E M A X I M U M R A T I N G S
(Note 1)
SYMBOL
V
DD
V5
SLEEP
MUTE
T
STORE
T
A
T
J
Supply Voltage
Input Section Supply Voltage
SLEEP Input Voltage
MUTE Input Voltage
Storage Temperature Range
Operating Free-air Temperature Range
Junction Temperature
PARAMETER
Value
16
6.0
-0.3 to 6.0
-0.3 to V5+0.3
-40 to 150
0 to 70
150
UNITS
V
V
V
V
°C
°C
°C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: See Power Dissipation Derating in the Applications Information section.
O P E R A T I N G C O N D I T I O N S
(Note 4)
SYMBOL
V
DD
V
IH
V
IL
Supply Voltage
High-level Input Voltage (MUTE, SLEEP)
Low-level Input Voltage (MUTE, SLEEP)
PARAMETER
MIN.
8.5
3.5
1
TYP.
12
MAX.
14.0
UNITS
V
V
V
Note 3: Recommended Operating Conditions indicate conditions for which the device is functional. See
Electrical Characteristics for guaranteed specific performance limits.
THERMAL CHARACTERISTICS
SYMBOL
θ
JC
θ
JA
PARAMETER
Junction-to-case Thermal Resistance
Junction-to-ambient Thermal Resistance (still air)
VALUE UNITS
2.5
50
°
C/W
°
C/W
2
TA2024C –KL/1.0/01.06
Tri path Technol og y, I nc. - Techni cal I nformation
ELECTRICAL CHARACTERISTICS
See Test/Application Circuit. Unless otherwise specified, V
DD
= 12V, f = 1kHz, Measurement
Bandwidth = 22kHz, R
L
= 4
Ω
, T
A
= 25
°
C, Package heat slug soldered to 2.8 square-inch PC pad.
SYMBOL
P
O
PARAMETER
Output Power
(Continuous Average/Channel)
CONDITIONS
THD+N = 0.1%
THD+N = 10%
I
DD,MUTE
I
DD, SLEEP
I
q
THD + N
IHF-IM
SNR
CS
PSRR
η
V
OFFSET
V
OH
V
OL
e
OUT
Mute Supply Current
Sleep Supply Current
Quiescent Current
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
Signal-to-Noise Ratio
Channel Separation
Power Supply Rejection Ratio
Power Efficiency
Output Offset Voltage
High-level output voltage
(FAULT & OVERLOAD)
Low-level output voltage
(FAULT & OVERLOAD)
Output Noise Voltage
MUTE = V
IH
SLEEP = V
IH
V
IN
= 0 V
P
O
= 9W/Channel
19kHz, 20kHz, 1:1 (IHF)
A-Weighted, P
OUT
= 15W, R
L
= 4Ω
f = 1 kHz
20 Hz
<
f
<
20 kHz
VDD = 9V to 13.2V
Vripple = 100mVrms, f=1kHz
P
OUT
= 10W/Channel, R
L
= 8Ω
No Load, MUTE = Logic Low
3.5
1
A-Weighted, input AC grounded
100
50
65
R
L
= 4Ω
R
L
= 8Ω
R
L
= 4Ω
R
L
= 8Ω
MIN.
9
5.5
12
8
TYP.
11
6
15
10
25
0.25
61
0.03
0.10
98
85
60
75
65
90
50
150
0.5
TBD
2
75
MAX.
UNITS
W
W
W
W
mA
mA
mA
%
%
dB
dB
dB
dB
dB
%
mV
V
V
µV
Note: Minimum and maximum limits are guaranteed but may not be 100% tested.
3
TA2024C –KL/1.0/01.06
Tri path Technol og y, I nc. - Techni cal I nformation
PIN DESCRIPTION
Pin
2, 3
Function
DCAP2, DCAP1
Description
Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted
10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
Digital 5VDC, Analog 5VDC
Analog Ground
Internal reference voltage; approximately 1.0 VDC.
A logic low output indicates the input signal has overloaded the amplifier.
Input stage output pins.
Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with
approximately 2.4VDC bias.
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. This pin should be tied to GND if not used. Unlike previous
Tripath devices, the input bias is still active, even if the MUTE pin is tied to a logic
high.
Input stage bias voltage (approximately 2.4VDC).
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
Power Grounds (high current)
Digital Ground. Connect to AGND locally (near the TA2024C).
Bridged output pairs
Supply pins for high current H-bridges, nominally 12VDC.
Not connected. Not bonded internally.
Analog 12VDC
Charge pump output (nominally 10V above VDDA)
Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
4, 9
5, 8,
17
6
7
10, 14
11, 15
12
V5D, V5A
AGND1, AGND2,
AGND3
REF
OVERLOADB
OAOUT1, OAOUT2
INV1, INV2
MUTE
16
18
19
20, 35
22
24, 27;
31, 28
25, 26,
29, 30
13, 21,
23, 32,
34
33
36
1
BIASCAP
SLEEP
FAULT
PGND2, PGND1
DGND
OUTP2 & OUTM2;
OUTP1 & OUTM1
VDD2, VDD2
VDD1, VDD1
NC
VDDA
CPUMP
5VGEN
TA2024C PINOUT
36-pin Power SOP Package
(Top View)
+5VGEN
DCAP2
DCAP1
V5D
AGND1
REF
OVERLOADB
AGND2
V5A
OAOUT1
INV1
MUTE
NC
OAOUT2
INV2
BIASCAP
AGND3
SLEEP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
CPUMP
PGND1
NC
VDDA
NC
OUTP1
VDD1
VDD1
OUTM1
OUTM2
VDD2
VDD2
OUTP2
NC
DGND
NC
PGND2
FAULT
4
TA2024C –KL/1.0/01.06
Tri path Technol og y, I nc. - Techni cal I nformation
APPLICATION /TEST CIRCUIT
TA2024C
C
I
2.2uF
+
OAOUT1
10
R
F
20KΩ
INV1
11
VDD1
L
o
10uH, 2A
31
OUTP1
R
I
20KΩ
C
A
0.1uF
(Pin 8)
5V
D
O
BIASCAP
16
5V
Processing
&
Modulation
PGND1
VDD1
(Pin 35)
(Pin 35)
L
o
10uH, 2A
*C
o
0.47uF
C
Z
0.22uF
C
DO
0.01uF
R
L
4Ω or *8Ω
28
OUTM1
D
O
(Pin 35)
*C
o
0.47uF
R
Z
10Ω, 1/2W
MUTE
12
PGND1
19
OAOUT2
14
R
F
20KΩ
INV2
7
VDD2
FAULT
OVERLOADB
C
I
2.2uF
+
15
R
I
20KΩ
24
OUTP2
D
O
REF
L
o
10uH, 2A
6
(Pin 8)
R
REF
8.25KΩ, 1%
Processing
&
Modulation
PGND2
VDD2
(Pin 20)
(Pin 20)
L
o
10uH, 2A
*C
o
0.47uF
C
Z
0.22uF
C
DO
0.01uF
3
+12V
1MΩ
C
D
0.1uF
DCAP1
27
OUTM2
D
O
R
Z
*C
o
0.47uF 10Ω, 1/2W
R
L
4Ω or *8Ω
2
18
DCAP2
PGND2
SLEEP
CPUMP
36
(Pin 20)
0.1uF
C
S
0.1uF
To Pin 1
4
5
9
C
S
0.1uF
+
V5D
AGND1
V5A
AGND2
AGND3
5V
VDDA
DGND
+5VGEN
VDD1
VDD1
PGND1
33
22
1
30
29
35
25
26
20
C
P
1uF
C
S
0.1uF
C
S
0.1uF
To Pins 4,9
8
17
C
SW
0.1uF
C
SW
180uF, 16V
+
VDD (+12V)
13
21
23
32
34
VDD2
NC
VDD2
PGND2
C
SW
0.1uF
+
C
SW
180uF, 16V
Note: Analog and Digital/Power Grounds must
be connected locally at the TA2024B
Analog Ground
Digital/Power Ground
All Diodes Motorola MBRS130T3
* Use C
o
= 0.22µF for 8 Ohm loads
5
TA2024C –KL/1.0/01.06
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