DATA SHEET
1GB Registered DDR SDRAM DIMM
HB54R1G9F2-A75B/B75B/10B (128M words
×
72 bits, 2 Banks)
Description
The HB54R1G9F2 is a 128M
×
72
×
2 bank Double
Data Rate (DDR) SDRAM Module, mounted 36 pieces
of 256Mbits DDR SDRAM (HM5425401BTB) sealed in
TCP package, 1 piece of PLL clock driver, 2 pieces of
register driver and 1 piece of serial EEPROM (2k bits
EEPROM) for Presence Detect (PD). Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 2-bit prefetch-pipelined architecture. Data
strobe (DQS) both for read and write are available for
high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. An outline of
the products is 184-pin socket type package (dual lead
out). Therefore, it makes high density mounting
possible without surface mount technology. It provides
common data inputs and outputs.
Decoupling
capacitors are mounted beside each TCP on the
module board.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Features
•
184-pin socket type package (dual lead out)
Outline: 133.35mm (Length)
×
43.18mm (Height)
×
4.80mm (Thickness)
Lead pitch: 1.27mm
•
2.5V power supply (VCC/VCCQ)
•
SSTL-2 interface for all inputs and outputs
•
Clock frequency: 143MHz/133MHz/125MHz (max.)
•
Data inputs and outputs are synchronized with DQS
•
4 banks can operate simultaneously and
independently (Component)
•
Burst read/write operation
•
Programmable burst length: 2, 4, 8
Burst read stop capability
•
Programmable burst sequence
Sequential
Interleave
•
Start addressing capability
Even and Odd
•
Programmable /CAS latency (CL): 3, 3.5
•
8192 refresh cycles: 7.8µs (8192/64ms)
•
2 variations of refresh
Auto refresh
Self refresh
Document No. E0089H40 (Ver. 4.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2001-2002
Hitachi,
Ltd. 2000
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB54R1G9F2-A75B/B75B/10B
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
CB0 to CB7
/RAS
/CAS
/WE
/S0, /S1
CKE0, CKE1
CK0
/CK0
DQS0 to DQS8
DM0 to DM8/DQS9 to DQS17
SCL
SDA
SA0 to SA2
VCC
VCCQ
VCCSPD
VREF
VSS
VCCID
/RESET
NC
Function
Address input
Row address
Column address
A0 to A12
A0 to A9, A11
Bank select address
Data input/output
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input and output data strobe
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for DQ circuit
Power for serial EEPROM
Input reference voltage
Ground
VCC identification flag
Reset pin (forces register inputs low)
No connection
Data Sheet E0089H40 (Ver. 4.0)
4
HB54R1G9F2-A75B/B75B/10B
Serial PD Matrix*
Byte No.
0
1
2
3
4
5
6
7
8
9
1
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM banks
Module data width
Module data width continuation
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
1
0
Bit5 Bit4
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
Bit3
0
1
0
1
1
0
1
0
0
0
0
0
Bit2
0
0
1
1
0
0
0
0
1
0
1
0
Bit1 Bit0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
Hex value
80
08
07
0D
0B
02
48
00
04
70
75
80
Comments
128
256 byte
SDRAM DDR
13
11
2
72 bits
0 (+)
SSTL 2.5V
CL = 2.5*
5
Voltage interface level of this assembly 0
DDR SDRAM cycle time, CL = X
-A75B
-B75B
-10B
0
0
1
10
SDRAM access from clock (tAC)
-A75B/B75B
-10B
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
75
80
02
82
04
04
01
0E
04
0C
01
02
26
C0
75
A0
0.75ns*
0.8ns*
5
ECC
5
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at
CLX - 0.5
-A75B
-B75B/10B
7.8 µs
Self refresh
×
4
×
4
1 CLK
2, 4, 8
4
2, 2.5
0
1
Registered
± 0.2V
CL = 2*
5
24
Maximum data access time (tAC) from
0
clock at CLX - 0.5
-A75B/B75B
-10B
1
Minimum clock cycle time at
0
CLX - 1
Maximum data access time (tAC) from
0
clock at CLX - 1
Minimum row precharge time (tRP)
0
1
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
75
80
00
00
50
0.75ns*
0.8ns*
5
5
25
26
27
20ns
Data Sheet E0089H40 (Ver. 4.0)
5
FPGA/CPLD
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