LH5PV16256
FEATURES
•
262,144 words
×
16 bit organization
•
Power supply: +3.0
±
0.15 V
•
Access time: 120 ns (MAX.)
•
Cycle time: 190 ns (MIN.)
•
Power consumption (MAX.):
126 mW (Operating)
94.5
µW
(Standby = CMOS input level)
220.5
µW
(Self-refresh = CMOS input level)
•
LVTTL compatible I/O
•
Available for address refresh,
auto-refresh, and self-refresh modes
•
2,048 refresh cycles/32 ms
•
Address non-multiple
•
Available for byte write mode using UWE
and LWE pins
•
Package:
44-pin, TSOP (Type II)
•
Process: Silicon-gate CMOS
•
Operating temperature: 0 - 70°C
•
Not designed or rated as radiation
hardened
CMOS 4M (256K
×
16) Pseudo-Static RAM
DESCRIPTION
The LH5PV16256 is a 4M bit Pseudo-Static RAM with
a 262,144 words
×
16 bit organization.
PIN CONNECTIONS
44-PIN TSOP (Type II)
TOP VIEW
LWE
UWE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
17
CS
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GND
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
I/O
8
V
CC
V
CC
RFSH
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
OE
GND
5PV16256S-1
Figure 1. Pin Connections
1
LH5PV16256
CMOS 4M (256
×
16) Pseudo-Static RAM
UWE 2
LWE 1
23 GND
44 GND
35 V
CC
34 V
CC
A
7
21
A
8
20
A
9
19
A
10
18
A
11
17 A -
0
COLUMN
A
12
16 A
6
ADDRESS
A
13
15
BUFFER
A
14
14
A
15
13
A
16
12
A
17
10
A
6
A
5
A
4
A
3
A
2
A
1
ROW
9
ADDRESS
8 A
7
- BUFFER
A
17
7
6
REFRESH
5
ADDRESS
COUNTER
4
V
BB
GENERATOR
25 I/O
0
COLUMN
DECODER
26 I/O
1
27 I/O
2
28 I/O
3
SENSE
AMPS
I/O
SELECTOR
DATA
IN
BUFFER
29 I/O
4
30 I/O
5
31 I/O
6
32 I/O
7
36 I/O
8
EXT/INT
ADDRESS
MUX.
ROW
DECODER
MEMORY
ARRAY 8M
DATA
OUT
BUFFER
37 I/O
9
38 I/O
10
39 I/O
11
40 I/O
12
41 I/O
13
42 I/O
14
43 I/O
15
A
0
3
CS 11
CE 22
CLOCK
GENERATOR
REFRESH
CONTROLLER
REFRESH
TIMER
RFSH 33
OE 24
5PV16256S-2
Figure 2. LH5PV16256 Block Diagram
PIN DESCRIPTION
PIN NAME
FUNCTION
PIN NAME
FUNCTION
A
7
- A
17
A
0
- A
6
UWE, LWE
OE
RFSH
CE
Row address input
Column address input
Upper/lower write enable input
Output enable input
Refresh input
Chip enable input
CS
I/O
8
- I/O
15
I/O
0
- I/O
7
V
CC
GND
Chip select input
Upper byte data input/output
Lower byte data input/output
Power supply
Ground
2
CMOS 4M (256
×
16) Pseudo-Static RAM
LH5PV16256
TRUTH TABLE
CE
CS
RFSH
OE
UWE
LWE
MODE
I/O
0 - 7
I/O8 - 15
L
H
H
L
H
H
H
L
H
L
H
X
X
X
Write
Word Read
Lower byte write
Upper byte write
Word write
Invalid
Auto refresh
CS standby
Standby
Output data
Input data
Don’t care
Input data
High-Z
High-Z
High-Z
High-Z
Output data
Don’t care
Input data
Input data
High-Z
High-Z
High-Z
High-Z
L
H
H
X
L
L
H
H
L
H
X
L
X
L
H
H
X
X
X
X
X
X
NOTES:
H = High
L = Low
X = Don’t care
REQUIREMENTS
2WE control
Please do not separate the UWE and LWE operation timing intentionally in the same write cycles. Each of the
UWE/LWE should satisfy the timing specifications individually.
Refresh after self-refresh or data retention mode
•
If address refresh is used during normal read/write cycles, the first address refresh must be executed within
15
µs
after self-refresh or data retention mode ends and the address refresh must be executed continuously for
2,048 refresh cycles.
•
If distributed auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within
15
µs
after self-refresh or data retention mode ends.
•
If burst auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within
15
µs
after self-refresh or data retention mode ends, and the auto-refresh must be executed continuously for
2,048 refresh cycles.
Bypass capacitor for power supply noise reduction
Because a PSRAM operates dynamically like a DRAM, it is recommended to put bypass capacitors between V
CC
and GND to absorb power supply noise due to the peak current.
3
LH5PV16256
CMOS 4M (256
×
16) Pseudo-Static RAM
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
Output short circuit current
Power dissipation
Operating temperature
Storage temperature
V
T
I
O
P
D
T
OPR
T
STG
-0.5 to +4.6
50
600
0 to +70
-65 to +150
V
mA
mW
°C
°C
1
NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Supply voltage
Input voltage
V
CC
GND
V
IH
V
IL
2.85
0
2.0
-0.3
3.0
0
3.15
0
V
CC
+ 0.3
0.8
V
V
V
V
1
1
NOTE:
1. The supply voltage with all V
CC
pins must be on the same level. The supply voltage with all GND pins must be on the same level.
PIN CAPACITANCE (T
A
= 0 to +70°C, f = 1 MHz, V
CC
= 3.0 V
±
0.15 V)
PARAMETER
CONDITIONS
SYMBOL
MIN.
MAX.
UNIT
A
0
- A
17
Input capacitance
UWE, LWE
OE, RFSH
CE, CS
Input/output capacitance
I/O
0
- I/O
15
C
IN1
C
IN2
C
IN3
C
OUT1
8
8
8
10
pF
pF
pF
pF
DC ELECTRICAL CHARACTERISTICS (T
A
= 0 to +70°C, V
CC
= 3.0 V
±
0.15 V)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Operating current in normal operation
Standby current
I
CC1
I
CC2
tRC = t
RC
(MIN.)
CE, RFSH = V
IH
(MIN.)
CE, RFSH = V
CC
- 0.2 V
CE = V
IH
(MIN.)
RFSH = V
IL
(MAX.)
CE = V
CC
- 0.2 V,
RFSH = 0.2 V
0 V
≤
V
IN
≤
6.5 V
0 V on all other pins
0 V
≤
V
OUT
≤
V
CC
+ 0.3 V
Input/output pins in High-Z
state
I
OUT
= -1 mA
I
OUT
= -100
µA
I
OUT
= 1 mA
I
OUT
= 100
µA
-10
-10
2.4
V
CC
- 0.2
2.2
40
1
30
1
70
10
10
0.4
0.2
3.15
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
V
1, 2
1
1
1
1
Self-refresh average current
I
CC3
Input leakage current
Output leakage current
I
LI
I
LO
V
OH
V
OL
V
R
Output HIGH voltage
Output LOW voltage
Data retention voltage
NOTES:
1. The input/output pins are in high impedance state.
2. I
CC1
depends on the cycle time.
4
CMOS 4M (256
×
16) Pseudo-Static RAM
LH5PV16256
AC ELECTRICAL CHARACTERISTICS
1,2,7
(T
A
= 0 to +70°C, V
CC
= 3.0 V
±
0.15 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTES
Random read, write cycle time
Random modify write cycle time
CE pulse width
CE precharge time
Address setup time
Row address hold time from CE
Column address hold time from CE
CS setup time from CE
CS hold time from CE
Read command setup time
Read command hold time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
Write disable to output in Low-Z
Chip disable to output in High-Z
Output disable to output in High-Z
WE to output in High-Z
Write command pulse width
Write command setup time
Write command hold time
Data setup time from write disable
Data setup time from chip disable
Data hold time from write disable
Data hold time from chip disable
Data hold time from column address
Column address hold time from chip disable
Column address hold time from write disable
Transition time (rise and fall)
Output disable setup time
Output disable hold time
Refresh time interval (2048 cycle)
Auto refresh cycle time
Refresh delay time from CE
Refresh pulse width (Auto refresh)
Refresh precharge time (Auto refresh)
CE delay time from refresh enable
(Auto refresh)
Refresh pulse width (Self refresh)
CE delay time from refresh precharge
(Self refresh)
V
CC
recovery time from data retention
Refresh setup hold time
Refresh disable hold time
Chip disable delay time from RFSH
t
RC
t
RMW
t
CE
t
P
t
AS
t
RAH
t
CAH
t
CSS
t
CSH
t
RCS
t
RCH
t
CEA
t
OEA
t
CLZ
t
OLZ
t
WLZ
t
CHZ
t
OHZ
t
WHZ
t
WCP
t
WCS
t
WCH
t
DSW
t
DSC
t
DHW
t
DHC
t
OH
t
AHC
t
AHW
t
T
t
ODS
t
ODH
t
REF
t
FC
t
RFD
t
FAP
t
FP
t
FCE
t
FAS
t
FRS
t
R
t
FS
t
RDH
t
RDD
190
250
120
60
0
30
120
0
30
0
0
20
0
0
0
0
0
35
35
120
30
30
0
30
0
20
0
3
0
15
190
90
80
40
190
8,000
600
5
0
15
15
10,000
120
60
30
30
30
10,000
10,000
50
32
1,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
3
3
11
9
4
4
11
9, 13
13
10, 13
12, 13
5, 12, 13
5
5, 11, 13
5
5
5, 13
6
6
8
8
5
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