CEP62A2/CEB62A2
N-Channel Enhancement Mode Field Effect Transistor
FEATURES
20V, 55A, R
DS(ON)
= 10mΩ @V
GS
= 4.5V.
R
DS(ON)
= 14mΩ @V
GS
= 2.5V.
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handing capability.
Lead free product is acquired.
TO-220 & TO-263 package.
D
D
G
S
CEB SERIES
TO-263(DD-PAK)
G
G
D
S
CEP SERIES
TO-220
S
ABSOLUTE MAXIMUM RATINGS
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
Drain Current-Pulsed
a
Tc = 25 C unless otherwise noted
Symbol
V
DS
V
GS
I
D
I
DM
P
D
T
J
,T
stg
Limit
20
Units
V
V
A
A
W
W/ C
C
±
12
55
220
54
0.36
-55 to 175
Maximum Power Dissipation @ T
C
= 25 C
- Derate above 25 C
Operating and Store Temperature Range
Thermal Characteristics
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Symbol
R
θJC
R
θJA
Limit
2.8
62.5
Units
C/W
C/W
Specification and data are subject to change without notice .
1
Rev 1. 2006.January
http://www.cetsemi.com
CEP62A2/CEB62A2
Electrical Characteristics
Parameter
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics
Static Drain-Source
On-Resistance
Dynamic Characteristics
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
b
c
c
b
Tc = 25 C unless otherwise noted
Symbol
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(on)
Test Condition
V
GS
= 0V, I
D
= 250µA
V
DS
= 20V, V
GS
= 0V
V
GS
= 12V, V
DS
= 0V
V
GS
= -12V, V
DS
= 0V
V
GS
= V
DS
, I
D
= 250µA
V
GS
= 4.5V, I
D
= 25A
V
GS
= 2.5V, I
D
= 25A
V
DS
= 10V, I
D
= 25A
V
DS
= 10V, V
GS
= 0V,
f = 1.0 MHz
0.5
7
10
35
2800
520
380
17
V
DD
= 15V, I
D
= 25A,
V
GS
= 5V, R
GEN
= 5.6Ω
16
68
31
V
DS
= 15V, I
D
= 50A,
V
GS
= 5V
31
4.6
10
55
V
GS
= 0V, I
S
= 25A
0.9
1.2
35
33
140
65
40
Min
20
1
100
-100
1.2
10
14
Typ
Max
Units
V
µA
4
nA
nA
V
mΩ
mΩ
S
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
A
V
Gate Threshold Voltage
Forward Transconductance
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
Drain-Source Diode Characteristics and Maximun Ratings
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
c.Guaranteed by design, not subject to production testing.
2
CEP62A2/CEB62A2
40
V
GS
=4.5,4.0,3.5,3.0V
30
100
25 C
I
D
, Drain Current (A)
I
D
, Drain Current (A)
V
GS
=2.5V
80
60
20
V
GS
=2.0V
10
40
20
T
J
=125 C
0
-55 C
V
GS
=1.5V
0
0
1
2
3
4
0
1
2
3
V
DS
, Drain-to-Source Voltage (V)
Figure 1. Output Characteristics
3600
3000
2400
1800
1200
600
0
0
5
10
15
Coss
Crss
20
25
Ciss
2.2
1.9
1.6
1.3
1.0
0.7
0.4
-100
V
GS
, Gate-to-Source Voltage (V)
Figure 2. Transfer Characteristics
R
DS(ON),
Normalized
R
DS(ON)
, On-Resistance(Ohms)
I
D
=25A
V
GS
=4.5V
C, Capacitance (pF)
-50
0
50
100
150
200
V
DS
, Drain-to-Source Voltage (V)
Figure 3. Capacitance
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
-50
T
J
, Junction Temperature( C)
Figure 4. On-Resistance Variation
with Temperature
V
GS
=0V
2
V
TH
, Normalized
Gate-Source Threshold Voltage
V
DS
=V
GS
I
D
=250µA
I
S
, Source-drain current (A)
25
50
75
100
125
150
10
10
1
10
-25
0
0
0.4
0.6
0.8
1.0
1.2
1.4
T
J
, Junction Temperature( C)
Figure 5. Gate Threshold Variation
with Temperature
V
SD
, Body Diode Forward Voltage (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
CEP62A2/CEB62A2
V
GS
, Gate to Source Voltage (V)
10
V
DS
=15V
I
D
=50A
10
3
I
D
, Drain Current (A)
8
R
DS(ON)
Limit
10
2
4
100µs
6
4
10
1
1ms
10ms
T
C
=25 C
T
J
=175 C
Single Pulse
10
-1
2
DC
0
1
2
0
0
15
30
45
60
10
0
10
10
10
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
V
DS
, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
V
DD
t
on
V
IN
D
V
GS
R
GEN
G
90%
t
off
t
r
90%
R
L
V
OUT
t
d(on)
V
OUT
t
d(off)
90%
10%
t
f
10%
INVERTED
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
r(t),Normalized Effective
Transient Thermal Impedance
10
0
D=0.5
0.2
10
-1
0.1
0.05
0.02
0.01
Single Pulse
P
DM
t
1
t
2
1. R
θJC
(t)=r (t) * R
θJC
2. R
θJC
=See Datasheet
3. T
JM-
T
C
= P* R
θJC
(t)
4. Duty Cycle, D=t1/t2
10
-2
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
Square Wave Pulse Duration (msec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
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