N-Channel Enhancement Mode Field Effect Transistor
FEATURES
100V, 13.3A, R
DS(ON)
= 115mΩ @V
GS
= 10V.
R
DS(ON)
= 125mΩ @V
GS
= 5V.
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handing capability.
Lead free product is acquired.
TO-251 & TO-252 package.
G
G
D
CED16N10L/CEU16N10L
PRELIMINARY
D
D
G
S
CEU SERIES
TO-252(D-PAK)
S
CED SERIES
TO-251(I-PAK)
S
ABSOLUTE MAXIMUM RATINGS
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
Drain Current-Pulsed
a
Tc = 25 C unless otherwise noted
Symbol
V
DS
V
GS
I
D
I
DM
P
D
T
J
,T
stg
Limit
100
Units
V
V
A
A
W
W/ C
C
±
20
13.3
53
43
0.34
-55 to 175
Maximum Power Dissipation @ T
C
= 25 C
- Derate above 25 C
Operating and Store Temperature Range
Thermal Characteristics
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Symbol
R
θJC
R
θJA
Limit
3.5
50
Units
C/W
C/W
Details are subject to change without notice .
1
Rev 1. 2010.Jan.
http://www.cetsemi.com
CED16N10L/CEU16N10L
Electrical Characteristics
Parameter
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics
Static Drain-Source
On-Resistance
Forward Transconductance
Dynamic Characteristics
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
b
c
c
b
Tc = 25 C unless otherwise noted
Symbol
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(on)
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
V
GS
= 0V, I
S
= 13.3A
VDS = 80V, ID = 13.3A,
VGS = 10V
Test Condition
V
GS
= 0V, I
D
= 250µA
V
DS
= 100, V
GS
= 0V
V
GS
= 20V, V
DS
= 0V
V
GS
= -20V, V
DS
= 0V
V
GS
= V
DS
, I
D
= 250µA
V
GS
= 10V, I
D
= 6.5A
V
GS
= 5V, I
D
= 5A
V
DS
= 10V, I
D
= 6.5A
1
95
100
5
630
105
26
11
2.7
73
7.5
17
2.2
3.5
13.3
1.5
22
6
150
15
25
Min
100
1
100
-100
3
115
125
Typ
Max
Units
V
µA
nA
nA
V
mΩ
mΩ
S
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
A
V
Gate Threshold Voltage
V
DS
= 25V, V
GS
= 0V,
f = 1.0 MHz
V
DD
= 50V, I
D
= 13.3A,
V
GS
= 10V, R
GEN
= 25Ω
Drain-Source Diode Characteristics and Maximun Ratings
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
c.Guaranteed by design, not subject to production testing.
d. L=0.5mH, I
AS
=13.3A, VDD=25V, R
G
=25
Ω,
Starting T
J
=25 C
2
CED16N10L/CEU16N10L
20
V
GS
=10,8,6,5V
20
25 C
I
D
, Drain Current (A)
I
D
, Drain Current (A)
15
V
GS
=4.0V
15
10
10
5
5
T
J
=125 C
-55 C
2.0
3.0
4.0
5.0
0
0
1
2
3
4
5
0
0.0
1.0
V
DS
, Drain-to-Source Voltage (V)
Figure 1. Output Characteristics
800
700
2.2
1.9
1.6
1.3
1.0
0.7
0.4
-100
V
GS
, Gate-to-Source Voltage (V)
Figure 2. Transfer Characteristics
C, Capacitance (pF)
Ciss
600
500
400
300
200
100
0
0
5
10
Coss
Crss
15
20
25
R
DS(ON),
Normalized
R
DS(ON)
, On-Resistance(Ohms)
I
D
=6.5A
V
GS
=10V
-50
0
50
100
150
200
V
DS
, Drain-to-Source Voltage (V)
Figure 3. Capacitance
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
-50
V
DS
=V
GS
T
J
, Junction Temperature( C)
Figure 4. On-Resistance Variation
with Temperature
I
S
, Source-drain current (A)
V
GS
=0V
10
1
V
TH
, Normalized
Gate-Source Threshold Voltage
I
D
=250µA
10
0
-25
0
25
50
75
100
125
150
10
-1
0.2
0.6
1.0
1.4
1.8
2.2
T
J
, Junction Temperature( C)
Figure 5. Gate Threshold Variation
with Temperature
V
SD
, Body Diode Forward Voltage (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
CED16N10L/CEU16N10L
V
GS
, Gate to Source Voltage (V)
10
8
6
4
2
0
V
DS
=80V
I
D
=13.3A
10
2
R
DS(ON)
Limit
I
D
, Drain Current (A)
100ms
10
1
1ms
10ms
DC
10
0
0
3
6
9
12
15
18
10
-1
T
C
=25 C
T
J
=175 C
Single Pulse
10
-1
10
0
10
1
10
2
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
V
DD
t
on
V
IN
V
GS
R
GEN
G
R
L
D
V
OUT
t
d(on)
V
OUT
10%
V
DS
, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
t
off
t
r
90%
t
d(off)
90%
10%
t
f
INVERTED
90%
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
r(t),Normalized Effective
Transient Thermal Impedance
10
0
D=0.5
0.2
10
-1
0.1
0.05
0.02
0.01
Single Pulse
P
DM
t
1
t
2
10
-2
1. R
θJC
(t)=r (t) * R
θJC
2. R
θJC
=See Datasheet
3. T
JM-
T
C
= P* R
θJC
(t)
4. Duty Cycle, D=t1/t2
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
Square Wave Pulse Duration (msec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
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