CEF09N6
Jul. 2002
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
600V , 6A ,R
DS(ON)
= 1.2
Ω
@V
GS
=10V.
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handling capability.
TO-220F full-pak for through hole.
D
6
G
G
D
S
TO-220F
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
-Pulsed
Drain-Source Diode Forward Current
Maximum Power Dissipation
@Tc=25 C
Derate above 25 C
Operating and Storage Temperature Range
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
STG
Limit
600
30
5
15
5
50
0.38
-55 to 150
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
R
JC
R
JA
6-127
2.6
65
C/W
C/W
CEF09N6
ELECTRICAL CHARACTERISTICS (T
C
25 C unless otherwise noted)
Parameter
Single Pulse Drain-Source
Avalanche Energy
Maximum Drain-Source
Avalanche Current
Symbol
a
Condition
V
DD
=50V, L=23.4mH
R
G
=25Ω
Min Typ Max Unit
DRAIN-SOURCE AVALANCHE RATING
6
E
AS
I
AS
500
9
mJ
A
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-Body Leakage
BV
DSS
I
DSS
I
GSS
V
GS(th)
R
DS(ON)
I
D(ON)
g
FS
b
V
GS
= 0V,I
D
= 250µA
V
DS
= 600V, V
GS
= 0V
V
GS
= 30V, V
DS
= 0V
V
DS
= V
GS
, I
D
= 250µA
V
GS
=10V, I
D
= 6A
V
GS
= 10V, V
DS
= 10V
V
DS
= 50V, I
D
= 6A
V
DD
= 200V,
I
D
= 9A,
V
GS
= 10V
R
GEN
=9.1
Ω
600
50
100
2
1.0
5
3
5
23
26
22
73
45
50
45
85
4
1.2
V
µA
nA
V
Ω
A
S
ns
ns
ns
ns
nC
nC
nC
ON CHARACTERISTICS
a
Gate Threshold Voltage
Drain-Source On-State Resistance
On-State Drain Current
Forward Transconductance
SWITCHING CHARACTERISTICS
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
t
D(ON)
t
r
t
D(OFF)
t
f
Q
g
Q
gs
Q
gd
105 165
V
DS
=480V, I
D
= 9A,
V
GS
=10V
6-128
6.0
45
CEF09N6
ELECTRICAL CHARACTERISTICS (T
C
=25 C unless otherwise noted)
Parameter
DYNAMIC CHARACTERISTICS
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Diode Forward Voltage
C
ISS
C
OSS
C
RSS
V
SD
V
GS
= 0V, Is =9A
V
DS
=25V, V
GS
= 0V
f =1.0MH
Z
950
135
90
1.5
P
F
P
F
P
F
Symbol
Condition
Min Typ Max Unit
6
DRAIN-SOURCE DIODE CHARACTERISTICS
a
V
Notes
a.Pulse Test:Pulse Width 300 s, Duty Cycle 2%.
b.Guaranteed by design, not subject to production testing.
12
V
GS
=10,9,8,7V
10
20
25 C
I
D
, Drain Current(A)
8
6
4
I
D
, Drain Current (A)
15
-55 C
10
125 C
5
V
GS
=6V
V
GS
=5V
2
0
0
2
4
6
8
10
12
0
0
1
2
3
4
5
V
DS
, Drain-to-Source Voltage (V)
V
GS
, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
6-129
CEF09N6
1800
3.0
R
DS(ON)
, Normalized
Drain-Source On-Resistance
V
GS
=10V
2.5
2.0
1.5
25 C
1.0
0.5
0
-55 C
Tj=125 C
1500
C, Capacitance (pF)
1200
Ciss
900
600
300
0
0
Crss
5
10
15
20
25
6
Coss
0
5
10
15
20
25
V
DS
, Drain-to Source Voltage (V)
I
D
, Drain Current(A)
Figure 3. Capacitance
BV
DSS
, Normalized
Drain-Source Breakdown Voltage
Vth, Normalized
Gate-Source Threshold Voltage
1.30
1.20
1.10
1.0
0.90
0.80
0.70
0.60
-50 -25
0
25
50
75 100 125 150
V
DS
=V
GS
I
D
=250 A
Figure 4. On-Resistance Variation with
Drain Current and Temperature
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-50 -25
I
D
=250 A
0
25
50
75 100 125 150
Tj, Junction Temperature ( C)
Tj, Junction Temperature ( C)
Figure 5. Gate Threshold Variation
with Temperature
12
Figure 6. Breakdown Voltage Variation
with Temperature
20
g
FS
, Transconductance (S)
8
6
4
2
0
0
5
10
15
20
Is, Source-drain current (A)
10
V
DS
=50V
10
V
GS
=0V
1
0.1
0.4
0.8
1.2
1.6
2.0
I
DS
, Drain-Source Current (A)
V
SD
, Body Diode Forward Voltage (V)
Figure 7. Transconductance Variation
with Drain Current
6-130
Figure 8. Body Diode Forward Voltage
Variation with Source Current
CEF09N6
V
GS
, Gate to Source Voltage (V)
15
12
9
6
3
0
0
12 24
48 60 72
84
96 108
Qg, Total Gate Charge (nC)
100
D=0.01
V
DS
=480V
I
D
=9A
I
D
, Drain Current (A)
40
10
R
DS
(O
N)
Lim
it
10
10
1m
s
0
s
10
m
s
;1
D
C
1
V
GS
=20V
Tc=25 C
Single Pulse
1
10
00
m
s
0.1
6
100
500 1000
V
DS
, Drain-Source Voltage (V)
Figure 9. Gate Charge
Figure 10. Maximum Safe
Operating Area
V
DD
t
on
V
IN
D
V
GS
R
GEN
G
90%
t
off
t
r
90%
R
L
V
OUT
t
d(on)
V
OUT
t
d(off)
90%
10%
t
f
10%
INVERTED
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
2
r(t),Normalized Effective
Transient Thermal Impedance
1
D=0.5
0.2
0.1
0.1
0.05
0.02
0.01
Single Pulse
0.01
0.01
P
DM
t
1
t
2
1. R
JC
(t)=r (t) * R
JC
2. R
JC
=See Datasheet
3. T
JM-
T
C
= P* R
JC
(t)
4. Duty Cycle, D=t1/t2
1
10
100
1000
10000
0.1
Square Wave Pulse Duration (msec)
Figure 13. Normalized Thermal Transient Impedance Curve
6-131
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