DA9090B.001
January 14, 1998
MAS9090B
LOW VOLTAGE 14-BIT LINEAR CODEC
•
14-bit linear analog to digital and digital to analog converters
•
8-bit A-law or
µ-law
companded analog to digital and digital to
analog converters
DESCRIPTION
The MAS9090 is a high performance low power PCM CODEC and filter device tailored to implement the audio
front-end functions required by the low voltage/low power consumption digital terminals.
FEATURES
•
•
•
•
•
•
•
•
•
•
Single 2.7-3.6 V or 4.5-5.5 V supply selectable
-30°C to 85°C temperature operation range
11 mW operating power (typ. at 2.7V)
15 mW operating power (typ. at 3.0V)
27 mW operating power (typ. at 3.6V)
38 mW operating power (typ. at 5.0V)
Digital bandpass filters
±0.5
dB absolute gain accuracy (untrimmed)
28-pin SO and 44-pin TQFP packages
Pin compatible with ST5090 and ST5092
APPLICATIONS
•
•
•
•
GSM digital cellular telephones
Battery operated audio front-ends for DSPs
ISDN Terminals
CT2 and DECT digital cordless telephones
BLOCK DIAGRAM
MIC3-
MIC2-
MIC1-
MUX
PreAmp
TX
Gain
EN
PCM
A to D
Converter
DE
VS
MIC3+
MIC2+
MIC1+
TE
1
1
0...22.5 dB
1.5 dB step
Tone
Gain
Bandpass
Filter
Compressor
TX
Register
TX
MUX
Clock
Generator
Sidetone
Gain
MCLK
FS
Ring/Tone/DTMF
Generator
BE
BZ
4
0...-27 dB
3 dB step
Buzzer Control
OE1
2
-12.5...-27.5 dB
1 dB step
Serial
Control
Interface
EN
CO
CI
CS
CCLK
LO
SP1-
SP1+
RTE
RX Gain
(SP1/SP2)
Buffer
Amplifiers
PCM
D to A
Converter
SI
SE
3
3
+
+
Bandpass
Filter
Expander
RX
Register
RX
SP2-
SP2+
0...-30 dB
2 dB step
OE2
1
DA9090B.001
January 14, 1998
PIN CONFIGURATION
SO28
TQFP44
NC
VCCA
VCCP
NC
SP1-
SP1+
SP2-
SP2+
GNDP
RX
1
2
3
4
5
6
7
8
9
10
28 MIC3+
27 MIC3-
26 GNDA
25 MIC1+
24 MIC1-
23 MIC2+
22 MIC2-
21 LO
20 MCLK
19 FS
18 GND
17 TX
16 CO
15 VCC
12 13 14 15 16 17 18 19 20 21 22
N N C C C B V C T G N
C C C S I Z C O X N C
D
L
C
K
1
NC
SP1- 2
3
SP1
NC
4
SP2- 5
SP2
6
NC
7
GNDP 8
9
NC
10
RX
11
NC
33
32
31
30
29
28
27
26
25
24
23
MIC1-
NC
MIC2+
MIC2-
NC
NC
NC
LO
MCLK
FS
NC
V
C
N N C
C C P
V
C
C N N
A C C
M
I
C
3
+
M
I
C
3
-
M
G
I
N
C
D N 1
A C +
44 43 42 41 40 39 38 37 36 35 34
CCLK 11
CS
CI
BZ
12
13
14
PIN DESCRIPTION
Pin Name
Pin Number
SO28
TQFP44
1,4
1,4,7,9
11,12,13
22,23,27
28,29,32
35,39,40,
43,44
41
42
2
3
5
6
8
10
14
15
16
17
18
19
20
Type
Function
No connection.
VCCA
VCCP
SP1-
SP1+
SP2-
SP2+
GNDP
RX
CCLK
CS
CI
BZ
VCC
CO
TX
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
P
P
AO
AO
AO
AO
G
DI
DI
DI
DI
AO
P
DO
DO
GND
FS
18
19
21
24
G
DI
Positive power supply input for analog section.
Positive power supply input for speaker amplifiers.
Speaker 1 amplifier negative output.
Speaker 1 amplifier positive output.
Speaker 2 amplifier negative output.
Speaker 2 amplifier positive output.
Speaker amplifier.
Receive data input.
Control clock input. Shifts serially into CI and CO when CS is
low. CCLK is asynchronous with other system clocks.
Chip select input.
Control data input.
Buzzer driver output.
Positive power supply input for the digital section. VCCA,
VCCP AND VCC must be connected together.
Control data output.
Transmit data output. Data is shifted out on this during the
assigned transmit slots. Otherwise, TX is on high impedance
state.
Ground for the digital section.
Frame sync input. This 8kHz signal defines the start of the TX
and RX frames.
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DA9090B.001
January 14, 1998
PIN DESCRIPTION
Pin Name
MCLK
LO
MIC2-
MIC2+
MIC1-
MIC1+
GNDA
MIC3-
MIC3+
Pin Number
20
25
21
26
22
30
23
31
24
33
25
34
26
36
27
37
28
38
Type
DI
DO
AI
AI
AI
AI
G
AI
AI
Function
Master clock input. Must be 512, 1536, 2048 or 2560 kHz
Value of bit DO of CR1.
Negative differential input for MIC2.
Positive differential input for MIC2.
Negative differential input for MIC1.
Positive differential input for MIC1.
GNDA analog ground.
Negative differential input for MIC3.
Positive differential input for MIC3.
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Voltage at MIC
Current at any digital output
Voltage at any digital input
Storage Temperature
Symbol
V
CC
Conditions
V
CC
< 5.5V
V
CC
< 5.5V
Min
-1
-1
-55
Max
7.0
V
CC
+1
50
V
CC
+1
+125
Unit
V
V
mA
V
°
C
T
S
RECOMMENDED OPERATION CONDITIONS
Parameter
Supply Voltage
Operating Temperature
Symbol
V
CC
T
A
Conditions
3.0V mode (SV=0)
5.0V mode (SV=1)
Min
2.7
4.5
-30
Typ
3.0
5.0
Max
3.6
5.5
+85
Unit
V
v
°
C
AC, TESTING INPUT, OUTPUT WAVEFORM
IN PU T /O U T P UT
0.8 V cc
0.7 V cc
test po ints
AC testing: inputs are driven at 0.8Vcc
for a logic ’1’ and 0.2Vcc for a logic ’0’.
Timing measurements are made at
0.7Vcc for a ’1’ and 0.3 Vcc for a ’0’.
0.2 Vcc
0.3 Vcc
3
DA9090B.001
January 14, 1998
ELECTRICAL CHARACTERISTICS
x
Digital Inputs/Outputs
(V
CC
= 2.7-3.6V or 4.5-5.5V, T
A
= -30
°
C to +85
°
C, unless otherwise specified)
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input low current
Input high current
Output current
impedance
in
high
Symbol
VIL
VIH
VOL
VOH
IIL
IIH
IOZ
Conditions
All digital inputs DC
All digital inputs AC
All digital inputs DC
All digital inputs AC
All digital outputs, IL = 10µA
All digital outputs, IL = 2mA
All digital outputs, IL = 10µA
All digital outputs, IL = 2mA
Any digital input,
GND < V
IN
< V
IL
Any digital input,
V
IH
< V
IN
< V
CC
TX and CO
Min
Typ
Max
0.3V
CC
0.2V
CC
Unit
V
V
0.7V
CC
0.8V
CC
0.1
0.4
V
CC
-0.1
V
CC
-0.4
-10
-10
-10
V
V
10
10
10
µA
µA
µA
x
Analog Inputs/Outputs
(V
CC
= 2.7-3.6V or 4.5-5.5V, T
A
= -30
°
C to +85
°
C, unless otherwise specified)
Parameter
Input leakage
Input resistance
Load resistance
Load capacitance
Output resistance
Differential offset
voltage from SP1+ to SP1-
Load resistance
Load capacitance
Input resistance
Output resistance
Differential offset
voltage from SP2+ to SP2-
x
Power Dissipation
Symbol
I
MIC
R
MIC
R
LSP1
C
LSP1
R
OSP1
V
OSP1
R
LSP2
C
LSP2
R
MIC
R
OSP2
V
OSP2
Conditions
GND < V
MIC
< V
CC
(active mic)
GND < V
MIC
< V
CC
SP1+ to SP1-
SP1+ to SP1-
Steady zero PCM code applied
to RX, I = 1mA
Alternating zero PCM code
applied to RX, R
L
= 30 ohms
SP2+ to SP2-
SP2+ to SP2-
GND < V
MIC
< V
CC
Steady zero PCM code applied
to RX, I = 1mA
Alternating zero PCM code
applied to RX, R
L
= 30 ohms
Min
-100
50
30
Typ
±20
Max
+100
Unit
µA
kΩ
Ω
50
1.0
-100
30
50
50
1.0
-100
0
+100
0
+100
nF
Ω
mV
Ω
nF
kΩ
Ω
mV
(V
CC
= 2.7-3.6V or 4.5-5.5V, T
A
= -30
°
C to +85
°
C, unless otherwise specified)
Parameter
Power down current at 3.0V
Power down current at 5V
Power up current at 2.7V
Power up current at 3.0V
Power up current at 3.6V
Power up current at 5V
SP1 short circuit current
Symbol
I
CC0
I
CC0
I
CC1
I
CC1
I
CC1
I
CC1
I
SHORT
Conditions
CCLK, CI = 0.1V
CS = VCC - 0.1V
CCLK, CI = 0.1V
CS = VCC - 0.1V
SP1 and SP2 not loaded
SP1 and SP2 not loaded
SP1 and SP2 not loaded
SP1 and SP2 not loaded
Min
Typ
0.08
0.08
4
5
7.5
7.5
130
Max
10
10
6
8
12
20
Unit
µA
µA
mA
mA
mA
mA
mA
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DA9090B.001
January 14, 1998
TIMING SPECIFICATIONS
x
Master Clock Timing
Parameter
Frequency of MCLK
Symbol
f
MCLK
t
WHM
t
WLM
t
WHM
t
WLM
t
RM
t
FM
Conditions
programmable
Min
Typ
512
1536
2048
878
80
80
30
30
1074
Max
Unit
kHz
Period of MCLK high/low
f
MCK
= 512
Period of MCLK high
f
MCK
= 1536, 2048
Period of MCLK low
f
MCK
= 1536, 2048
Rise time of MCLK
Fall time of MCLK
x
PCM Interface Timing
Parameter
Hold time, MCLK low to FS low
Setup time, FS high to MCLK low
Delay time, MCLK high to valid TX data
Delay time, MCLK low to TX disabled
Delay time, FS high to valid TX data
Setup time, RX data valid to MCLK low
Hold time, MCLK low to invalid RX data
Hold time, MCLK high to FS low
Setup time, FS high to MCLK high
Delay time, MCLK low to valid TX data
Delay time, MCLK high to TX disabled
Hold time, MCLK high to invalid RX data
x
Non-Delayed Data Timing Diagram
t
HMLF
MCLK
1
2
3
Measured from V
IH
to V
IH
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
ns
ns
ns
ns
ns
Symbol
t
HMLF
t
SFML
t
DMHT
t
DMLZ
t
DFT
t
SRML
t
HMLR
t
HMHF
t
SFMH
t
DMLT
t
DMHZ
t
HMHR
Conditions
Min
17
30
Typ
Max
Unit
ns
ns
Load = 100pF
10
Load = 100pF
non-delayed mode only
20
10
30
30
Load = 100pF
10
20
100
100
100
ns
ns
ns
ns
ns
ns
ns
100
100
ns
ns
ns
t
RM
4
t
FM
5
t
WHM
6
7
8/16
t
SFML
FS
t
WLM
t
DFT
t
DMHT
TX
1
2
3
4
5
6
7
t
DMLZ
8/16
t
SRML
t
HMLR
RX
1
2
3
4
5
6
7
8/16
In companded mode the timing is applied to 8 bits instead of 16 bits.
5
FPGA/CPLD
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