give designers ultimate control of their code security
needs.
8 M-bit (512 kB x 16) SmartVoltage
Flash Memory
• Enhanced data protection features
– Absolute protection with V
PP
= GND
– Flexible block locking
– Block erase/word write lockout during power
transitions
• SRAM-compatible write interface
• High-density symmetrically-blocked architecture
– Sixteen 32 k-word erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 1.6 million block erase cycles/chip
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases I
CC
in static mode
• Automated word write and block erase
– Command user interface
– Status register
• ETOX
TM
∗
V nonvolatile flash technology
• Package
– 44-pin SOP (SOP044-P-0600)
∗
ETOX is a trademark of Intel Corporation.
FEATURES
• SmartVoltage technology
– 2.7 V, 3.3 V or 5 V V
CC
– 2.7 V, 3.3 V, 5 V or 12 V V
PP
• High performance read access time
LH28F800SG-L70
– 70 ns (5.0±0.25 V)/80 ns (5.0±0.5 V)/
85 ns (3.3±0.3 V)/100 ns (2.7 to 3.0 V)
LH28F800SG-L10
– 100 ns (5.0 ±0.5 V)/100 ns (3.3±0.3 V)/
120 ns (2.7 to 3.0 V)
• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
LH28F800SG-L (FOR SOP)
COMPARISON TABLE
VERSIONS
LH28F800SG-L
(FOR SOP)
LH28F800SG-L
∗
1
(FOR TSOP, CSP)
LH28F800SGH-L
∗
1
(FOR TSOP, CSP)
OPERATING TEMPERATURE
0 to +70˚C
0 to +70˚C
– 40 to +85˚C
PACKAGE
44-pin SOP
48-pin TSOP (I)
48-ball CSP
48-pin TSOP (I)
48-ball CSP
WRITE PROTECT FUNCTION
Controlled by RP# pin
Controlled by
WP# and RP# pins
Controlled by
WP# and RP# pins
∗
1 Refer to the datasheet of LH28F800SG-L/SGH-L (FOR TSOP, CSP).
PIN CONNECTIONS
44-PIN SOP
V
PP
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE#
GND
OE#
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
TOP VIEW
RP#
WE#
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
NC
GND
DQ
15
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
(SOP044-P-0600)
-2-
LH28F800SG-L (FOR SOP)
BLOCK DIAGRAMS
DQ
0
-DQ
15
OUTPUT
BUFFER
INPUT
BUFFER
OUTPUT
MULTIPLEXER
IDENTIFIER
REGISTER
DATA
REGISTER
I/O
LOGIC
V
CC
CE#
STATUS
REGISTER
COMMAND
USER
INTERFACE
WE#
OE#
RP#
DATA
COMPARATOR
A
0
-A
18
INPUT
BUFFER
Y DECODER
Y GATING
WRITE
STATE
MACHINE
RY/BY#
PROGRAM/ERASE
VOLTAGE SWITCH
V
PP
ADDRESS
LATCH
X DECODER
16
32 k-WORD
BLOCKS
V
CC
GND
ADDRESS
COUNTER
-3-
LH28F800SG-L (FOR SOP)
PIN DESCRIPTION
SYMBOL
A
0
-A
18
TYPE
INPUT
NAME AND FUNCTION
ADDRESS INPUTS :
Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS :
Inputs data and commands during CUI write cycles; outputs
DQ
0
-DQ
15
INPUT/
OUTPUT
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CHIP ENABLE :
Activates the device's control logic, input buffers, decoders, and sense
CE#
INPUT
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN :
Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
RP#
INPUT
power-down sets the device to read array mode. RP# at V
HH
allows to set permanent
lock-bit. Block erase, word write, or lock-bit configuration with V
IH
< RP# < V
HH
produce
spurious results and should not be attempted.
OE#
WE#
INPUT
INPUT
OUTPUT ENABLE :
Controls the device's outputs during a read cycle.
WRITE ENABLE :
Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY :
Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, word write, or lock-bit configuration).
RY/BY#
OUTPUT
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and word write is inactive, word write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.
BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :
For erasing array blocks, writing word, or configuring lock-bits. With V
PP
≤
V
PPLK
,
V
PP
SUPPLY
memory contents cannot be altered. Block erase, word write, and lock-bit configuration
with an invalid V
PP
(see
Section 6.2.3 "DC CHARACTERISTICS")
produce spurious
results and should not be attempted.
DEVICE POWER SUPPLY :
Internal detection configures the device for 2.7 V, 3.3 V or
5 V operation. To switch from one voltage to another, ramp V
CC
down to GND and then
V
CC
SUPPLY
ramp V
CC
to the new voltage. Do not float any power pins. With V
CC
≤
V
LKO
, all write
attempts to the flash memory are inhibited. Device operations at invalid V
CC
voltage
(see
Section 6.2.3 "DC CHARACTERISTICS")
produce spurious results and should
not be attempted.
GROUND :
Do not float any ground pins.
NO CONNECT :
Lead is not internal connected; recommend to be floated.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
