UM61512A Series
64K X 8 BIT HIGH SPEED CMOS SRAM
Features
Single +5V power supply
Access times: 15/20/25ns (max.)
Current: Operating: 160mA (max.)
Standby: 10mA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL compatible
Common I/O using three-state output
Output enable and two chip enable inputs for easy
application
Data retention voltage: 3V (min.)
Available in 32-pin SKINNY DIP, TSOP, SOP, SOJ
and both 300/400 mil packages
General Description
The UM61512A is a low operating current 524,288-bit
static random access memory organized as 65,536
words by 8 bits and operates on a single 5V power
supply. It is built using UMC's high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 3V.
Pin Configurations
SKINNY/SOJ/SOP
1
2
3
4
5
6
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
17
32
16
1
TSOP (forward type)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
NC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
GND
32
31
30
29
28
27
Pin
Name
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
NC
A14
A12
A7
A6
A5
A4
Pin No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin
Name
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
GND
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
CE1
A10
OE
UM61512AV
UM61512A
7
8
9
10
11
12
13
14
15
16
26
25
24
23
22
21
20
19
18
17
1
UM61512A
Block Diagram
A0
VCC
GND
512 X 2048
DECODER
A13
A14
A15
MEMORY ARRAY
I/O
1
INPUT
DATA
CIRCUIT
I/O
8
COLUMN I/O
CE2
CE1
OE
WE
CONTROL
CIRCUIT
Pin Descriptions
Pin No.
1, 2
3 - 12, 23,
25 - 28, 31
13 - 15, 17 - 21
16
22
24
29
30
32
SKINNY/SOJ/SOP
Symbol
NC
A0 - A15
I/O
1
- I/O
8
GND
CE1
OE
WE
CE2
VCC
Description
No Connection
Address Inputs
Data Input/Outputs
Ground
Chip Enable
Output Enable
Write Enable
Chip Enable
Power Supply
Pin Description
Pin No.
1 - 4, 7,
11 - 20, 31
5
6
8
9, 10
21 - 23, 25 - 29
24
30
32
TSOP
Symbol
A0 - A15
WE
CE2
VCC
NC
I/O
1
- I/O
8
GND
CE1
OE
Description
Address Inputs
Write Enable
Chip Enable
Power Supply
No Connection
Data Input/Outputs
Ground
Chip Enable
Output Enable
2
UM61512A
Recommended DC Operating Conditions
A
= 0°C to + 70°C)
(T
Symbol
VCC
GND
V
IH
V
IL
C
L
TTL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Output Load
Output Load
Min.
4.75
0
2.2
-0.3
-
-
Typ.
5.0
0
3.5
0
-
-
Max.
5.25
0
VCC + 0.3
+0.8
30
1
Unit
V
V
V
V
pF
-
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC +0.5V
Operating Temperature, Topr . . . . . . . . . . 0
°C
to +70°C
Storage Temperature, Tstg . . . . . . . . . . -55
°C
to +125°C
Temperature Under Bias, Tbias . . . . . . . -10
°C
to +85°C
Power Dissipation, Pt . . . . . . . . . . . . . . . . . . . . . . 1.0W
Soldering Temp. & Time . . . . . . . . . . . . . 260
°C,
10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics
(T
A
= 0°C to + 70°C, VCC = 5V
±
5%, GND = 0V)
Symbol
Parameter
UM61512A-15/20/25
Min.
I
LI
I
LO
Input Leakage Current
Output Leakage Current
-
-
Max.
2
2
µA
µA
V
IN
= GND to VCC
CE1 = V
IH
or CE2 = V
IL
or
OE = V
IH
or WE = V
IL
V
I/O
= GND to VCC
CE1 = V
IL
, CE2 = V
IH
I
I/O
= 0 mA
CE1 = V
IH
or CE2 = V
IL
CE1
≥
VCC - 0.2V,
CE2
≥
VCC - 0.2V,
V
IN
≤
0.2V or V
IN
≥
VCC - 0.2V
Unit
Conditions
I
CC1
(1)
I
SB
I
SB1
Dynamic Operating Current
-
-
-
160
30
20
mA
mA
mA
Standby Power
Supply Current
I
SB2
-
20
mA
CE1
≤
0.2V, CE2
≤
0.2V
I
OL
= 8 mA
I
OH
= -4 mA
V
IN
≤
0.2V or V
IN
≥
VCC - 0.2V
V
OL
V
OH
Output Low Voltage
Output High Voltage
-
2.4
0.4
-
V
V
Note: 1. I
CC1
is dependent on output loading, cycle rates, and Read/Write patterns.
3
UM61512A
Truth Table
Mode
Standby
CE1
H
X
Output Disable
Read
Write
Note: X = H or L
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O Operation
High Z
High Z
High Z
D
OUT
D
IN
Supply Current
I
SB
, I
SB1
I
SB
, I
SB2
I
CC1
I
CC1
I
CC1
Capacitance
(T
A
= 25°C, f = 1.0 MHz)
Symbol
C
IN
*
C
I/O
*
Parameter
Input Capacitance
Input/Output Capacitance
Min.
Max.
8
10
Unit
pF
pF
Conditions
V
IN
= 0V
V
I/O
= 0V
* These parameters are sampled and not 100% tested.
AC Characteristics
(T
A
= 0°C to +70°C, VCC = 5V
±
10%)
Symbol
Parameter
UM61512A-15
Min.
Read Cycle
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
Output Disable to Output in High Z
Output Hold from Address Change
Output Enable to Output in Low Z
Chip Disable to Output in High Z
CE1
CE2
Output Enable to Output Valid
Chip Enable to Output in Low Z
CE1
CE2
Read Cycle Time
Address Access Time
Chip Enable Access Time
CE1
CE2
15
-
-
-
-
5
5
2
-
-
2
3
-
15
15
15
7
-
-
-
10
10
9
-
20
-
-
-
-
5
5
2
-
-
2
5
-
20
20
20
9
-
*
-
10
10
9
-
25
-
-
-
-
5
5
2
-
-
2
5
-
25
25
25
12
-
-
-
15
15
10
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max.
UM61512A-20
Min.
Max.
UM61512A-25
Min.
Max.
Unit
4
UM61512A
AC Characteristics (continued)
Symbol
Parameter
UM61512A-15
Min.
Write Cycle
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Write Cycle Time
Chip Enable to End of Write
Address Setup Time of Write
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
15
12
0
12
9
0
0
7
0
5
20
15
0
15
-
-
8
-
-
-
20
15
0
15
11
0
0
7
0
5
25
20
0
20
-
-
13
-
-
-
25
20
0
20
-
-
13
-
-
-
-
-
-
-
-
-
13
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max.
UM61512A-20
Min.
Max.
UM61512A-25
Min.
Max.
Unit
Notes: t
CHZ1
, t
CHZ2
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
Timing Waveforms
Read Cycle 1
(1,2,4)
t
RC
Address
t
AA
t
OH
t
OH
D
OUT
5
FPGA/CPLD
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