SRAM
Austin Semiconductor, Inc.
8K x 8 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-38294
• MIL-STD-883
MT5C6408
PIN ASSIGNMENT
(Top View)
A6
A7
A12
NC
Vcc
WE\
CE2\
4 3 2 1 28 27 26
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
25
24
23
22
21
20
19
A8
A9
A11
OE\
A10
CE1\
DQ7
28-Pin DIP (C)
(300 MIL)
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE\
CE2
A8
A9
A11
OE\
A10
CE1\
DQ8
DQ7
DQ6
DQ5
DQ4
28-Pin LCC (EC)
FEATURES
• High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns
• Battery Backup: 2V data retention
• High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE1\ and CE2
• All inputs and outputs are TTL compatible
12 13 14 15 16 17 18
28-Pin Flat Pack (F)
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Package(s)
Ceramic DIP (300 mil)
Ceramic LCC
Ceramic Flatpack
MARKING
-12
-15
-20
-25
-35
-45
-55*
-70*
Vcc
WE\
CE2
A8
A9
A11
OE\
A10
CE1\
DQ8
DQ7
DQ6
DQ5
DQ4
GENERAL DESCRIPTION
No. 108
No. 204
No. 302
The MT5C6408, 8K x 8 SRAM, employs high-speed,
low-power CMOS technology, eliminating the need for clocks
or refreshing. These SRAM’s have equal access and cycle
times.
For flexibility in high-speed memory applications,
Austin Semiconductor offers dual chip enables (CE1\, CE2) and
output enable (OE\) capability. These enhancements can place
the outputs in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.
Reading is accomplished when WE\ and CE2 remain HIGH and
CE1\ and OE\ go LOW. The device offers a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
These devices operate from a single +5V power sup-
ply and all inputs and outputs are fully TTL compatible.
C
EC
F
• Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
V
CC
Vss
MT5C6408
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
ROW DECODER
DQ8
I/O CONTROL
65,536-BIT
MEMORY ARRAY
DQ1
CE1\
CE2
COLUMN DECODER
OE\
WE\
A
8
A
9
A
10
A
11
A
12
POWER
DOWN
TRUTH TABLE
MODE
STANDBY
STANDBY
READ
READ
WRITE
CE1\
H
X
L
L
L
CE2
X
L
H
H
H
WE\
X
X
H
H
L
OE\
X
X
L
H
X
DQ
POWER
HIGH-Z STANDBY
HIGH-Z STANDBY
Q
ACTIVE
HIGH-Z ACTIVE
D
ACTIVE
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Input or DQ Relative to Vss........-0.5V to +7.0V
Voltage on Vcc Supply Relative to Vss.................-0.5V to +7.0V
Storage Temperature….........................................-65
o
C to +150
o
C
Power Dissipation......................................................................1W
Max Junction Temperature..................................................+175°C
Lead Temperature (soldering 10 seconds)........................+260
o
C
Short Circuit Output Current................................................50mA
MT5C6408
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
CONDITIONS
SYMBOL
V
IH
V
IL
IL
I
IL
O
V
OH
V
OL
MIN
2.2
-0.5
-10
-10
2.4
MAX
Vcc+0.5
0.8
10
10
0.4
UNITS
V
V
µA
µA
V
V
1
1
NOTES
1
1, 2
0V
≤
V
IN
≤
Vcc
Output(s) disabled
0V < V
OUT
< Vcc
I
OH
= -4.0mA
I
OL
= 8.0mA
PARAMETER
Power Supply
Current: Operating
CONDITIONS
CE\ < V
IL
; V
CC
= MAX
f = MAX = 1/t
RC
(MIN)
Output Open
CE\ > V
IH
; All Other Inputs
< V
IL
or > V
IH
, V
CC
= MAX
f = 0 Hz
CE\ > (V
CC
-0.2); V
CC
= MAX
All Other Inputs < 0.2V
or > (V
CC
- 0.2V), f = 0 Hz
SYM
I
cc
I
SBTSP
I
SBTLP
I
SBCSP
I
SBCLP
-12
180
-15
170
MAX
-20
-25
160
155
-35
155
-45
145
UNITS NOTES
mA
3
Power Supply
Current: Standby
40
30
20
10
40
30
20
10
40
30
20
10
40
30
20
10
40
30
20
10
40
30
20
10
mA
mA
mA
mA
CAPACITANCE
DESCRIPTION
Input Capacitance
Output Capacitance
CONDITIONS
T
A
= 25
o
C, f = 1MHz
Vcc = 5V
SYM
C
I
C
O
MAX
6
7
UNITS
pF
pF
NOTES
4
4
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
MT5C6408
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Output Enable access time
Output Enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
-12
-15
-20
-25
-35
-45
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
HZOE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
12
12
12
2
2
7
8
0
7
12
10
10
0
0
10
7
0
2
0
15
13
13
0
0
13
10
0
0
0
0
10
20
15
15
0
0
15
12
0
0
0
0
0
10
12
0
15
25
20
20
0
0
20
15
0
0
0
15
15
15
0
0
15
15
0
15
35
30
30
0
0
30
15
5
0
0
20
20
20
0
0
15
15
0
30
45
40
40
0
0
40
20
5
0
0
25
25
25
3
0
15
15
0
40
35
35
35
3
0
25
20
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
6, 7
6
7
10
10
15
15
25
7
6, 7
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
MT5C6408
167Ω
Q
30pF
V
TH
= 1.73V Q
167Ω
5pF
V
TH
= 1.73V
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. t
LZCE
, t
LZWE
, t
LZOE
, t
HZCE
, t
HZOE
and t
HZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
1.
2.
3.
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
and
t
HZOE
is less than t
LZOE
.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
t
RC = Read Cycle Time.
12. CE2 timing is the same as CE1\ timing. The waveform is
inverted.
13. Chip enable (CE1\, CE2) and write enable (WE\) can
initiate and terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CE\ > (V
CC
- 0.2V)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
I
CCDR
300
µA
CONDITIONS
SYM
V
DR
MIN
2
MAX
---
UNITS
V
NOTES
t
CDR
t
R
0
t
RC
---
ns
ns
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
CDR
DATA RETENTION MODE
4.5V
V
DR
> 2V
4.5V
t
R
V
DR
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
4321
4321
4321
4321
321
21
321
321
3
CE\
V
IH
V
IL
432
3216
87
432154321
321154321
87
876
422154321
321154321
4326
3316
87
987654321
4321
321
321
321
987654321
4321
4321
321
987654321
4321
987654321
DON’T CARE
UNDEFINED
FPGA/CPLD
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