Preliminary
‡
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Features
1/3-Inch Wide-VGA CMOS Digital Image
Sensor
MT9V032C12STM (Monochrome, Pb-Free)
MT9V032C12STC (Color, Pb-Free)
Features
•
• Array format: Wide-VGA, active 752H x 480V
(360,960 pixels)
• Global shutter photodiode pixels; simultaneous
integration and readout
• Monochrome or color: Near_IR enhanced
performance for use with non-visible NIR
illumination
• Readout modes: Progressive or interlaced
• Shutter efficiency: >99%
• Simple two-wire serial interface
• Register lock capability
• Window size: User programmable to any smaller
format (QVGA, CIF, QCIF, and so on). Data rate can
be maintained independent of window size
• Binning: 2 x 2 and 4 x 4 of the full resolution
• ADC: On-chip, 10-bit column-parallel (option to
operate in 12-bit to 10-bit companding mode)
• Automatic controls: Auto exposure control (AEC)
and auto gain control (AGC); variable regional and
variable weight AEC/AGC
• Support for four unique serial control register IDs to
control multiple imagers on the same bus
• Data output formats:
• Single sensor mode:
10-bit parallel/stand-alone
8-bit or 10-bit serial LVDS
• Stereo sensor mode:
Interspersed 8-bit serial LVDS
Micron
®
DigitalClarity
®
CMOS imaging technology
Table 1:
Key Performance Parameters
Value
1/3-inch
4.51mm(H) x 2.88mm(V)
5.35mm diagonal
752H x 480V
6.0µm x 6.0µm
Monochrome or color RGB
Bayer pattern
Global shutter—TrueSNAP™
26.6 MPS/26.6 MHz
Parameter
Optical format
Active imager size
Active pixels
Pixel size
Color filter array
Shutter type
Maximum data rate/
master clock
Full resolution
Frame rate
ADC resolution
Responsivity
Dynamic range
752 x 480
60 fps (at full resolution)
10-bit column-parallel
4.8 V/lux-sec (550nm)
>55dB linear;
>80
−
100dB in HiDy mode
Supply voltage
3.3V +0.3V
(
all supplies)
Power consumption
<320mW at maximum data
rate; 100µW standby current
Operating temperature –30°C to +70°C
Packaging
48-pin CLCC
Output gain
15.3 e-/LSB
Read noise
25 e-PRMS at 1X
Dark current
9,042 e-/pix/s at 55°C
Ordering Information
Table 2:
Available Part Numbers
Description
48-pin CLCC (mono)
48-pin CLCC (color)
Demo kit (mono)
Demo kit headboard only
(mono)
Demo kit (color)
Demo kit headboard only (color)
Applications
•
•
•
•
•
•
•
•
Security
High dynamic range imaging
Unattended surveillance
Stereo vision
Video as input
Machine vision
Automation
Traffic camera
Part Number
MT9V032C12STM ES
MT9V032C12STC ES
MT9V032C12STMD ES
MT9V032C12STMH ES
MT9V032C12STCD ES
MT9V032C12STCH ES
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MT9V032_LDS_1.fm - Rev. B 3/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Preliminary
‡
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
General Description
General Description
The Micron Imaging MT9V032 is a 1/3-inch wide-VGA format CMOS active-pixel digital
image sensor with global shutter and high dynamic range (HDR) operation. The sensor
has specifically been designed to support the demanding interior and exterior unat-
tended surveillance imaging needs, which makes this part ideal for a wide variety of
imaging applications in real-world environments.
This wide-VGA CMOS image sensor features DigitalClarity
⎯
Micron’s breakthrough
low-noise CMOS imaging technology that achieves CCD image quality (based on signal-
to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and
integration advantages of CMOS.
The active imaging pixel array is 752H x 480V. It incorporates sophisticated camera
functions on-chip—such as binning 2 x 2 and 4 x 4, to improve sensitivity when oper-
ating in smaller resolutions—as well as windowing, column and row mirroring. It is
programmable through a simple two-wire serial interface.
The MT9V032 can be operated in its default mode or be programmed for frame size,
exposure, gain setting, and other parameters. The default mode outputs a wide-VGA-
size image at 60 frames per second (fps).
An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. A 12-bit resolu-
tion companded for 10-bits for small signals can be alternatively enabled, allowing more
accurate digitization for darker areas in the image.
In addition to a traditional, parallel logic output the MT9V032 also features a serial low-
voltage differential signaling (LVDS) output. The sensor can be operated in a stereo-
camera mode, and the sensor, designated as a stereo-master, is able to merge the data
from itself and the stereo-slave sensor into one serial LVDS stream.
Figure 1:
Block Diagram
Serial
Register
I/O
Control
Register
Active-Pixel
Sensor
(APS)
Array
752H x 480V
Timing and
Control
Analog Processing
Parallel
Video
Data Out
ADCs
Digital Processing
Serial
Video
LVDS Out
Slave
Video LVDS In
(for stereo applications only)
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MT9V032_LDS_2.fm - Rev. B 3/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Preliminary
‡
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
General Description
Figure 2:
MT9V032 Quantum Efficiency vs. Wavelength
40
Blue
Green
(B)
Green
(R)
Red
35
30
Quantum E ffi
c
ien
c
y (%)
25
20
15
10
5
0
350
450
550
650
750
850
950
1050
Wavelength (nm)
PDF: 09005aef824c9998/Source: 09005aef824c999c
MT9V032_LDS_2.fm - Rev. B 3/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Preliminary
‡
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Pin Descriptions
Pin Descriptions
Figure 3 shows the package pinout for the MT9V032. Table 3 on page 5 provides the pin
descriptions.
Figure 3:
48-Pin CLCC Package Pinout Diagram
SER_DATAOUT_N
SER_DATAOUT_P
SHFT_CLKOUT_N
SHFT_CLKOUT_P
VDDLVDS
SYSCLK
PIXCLK
D
OUT
0
D
OUT
1
44
D
GND
6
5
4
3
2
1
48
47
46
45
D
OUT
2
43
42
41
40
39
38
37
36
35
34
33
32
31
V
DD
LVDSGND
BYPASS_CLKIN_N
BYPASS_CLKIN_P
SER_DATAIN_N
SER_DATAIN_P
LVDSGND
D
GND
V
DD
D
OUT
5
D
OUT
6
D
OUT
7
D
OUT
8
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D
OUT
3
D
OUT
4
VAAPIX
V
AA
A
GND
NC
NC
V
AA
A
GND
STANDBY
RESET#
S_CTRL_ADR1
FRAME_VALID
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MT9V032_LDS_2.fm - Rev. B 3/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
S_CTRL_ADR0
STFRM_OUT
LED_OUT
OE
D
OUT
9
STLN_OUT
LINE_VALID
EXPOSURE
S
DATA
RSVD
SCLK
Preliminary
‡
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Pin Descriptions
Table 3:
Pin Number
29
10
11
8
9
23
25
Pin Descriptions
Only pins D
OUT
0 through D
OUT
9 may be tri-stated
Symbol
RSVD
SER_DATAIN_N
SER_DATAIN_P
BYPASS_CLKIN_N
BYPASS_CLKIN_P
EXPOSURE
SCLK
Type
Input
Input
Input
Input
Input
Input
Input
Description
Connect to D
GND
.
Serial data in for stereoscopy (differential negative). Tie to
1kΩ pull-up (to 3.3V) in non-stereoscopy mode.
Serial data in for stereoscopy (differential positive). Tie to
D
GND
in non-stereoscopy mode.
Input bypass shift-CLK (differential negative). Tie to 1KΩ
pull-up (to 3.3V) in non-stereoscopy mode.
Input bypass shift-CLK (differential positive). Tie to D
GND
in non-stereoscopy mode.
Rising edge starts exposure in slave mode.
Two-wire serial interface clock. Connect to V
DD
with 1.5K
resistor even when no other two-wire serial interface
peripheral is attached.
D
OUT
enable pad, active HIGH.
Two-wire serial interface slave address bit 3.
Two-wire serial interface slave address bit 5.
Asynchronous reset. All registers assume defaults.
Shut down sensor operation for power saving.
Master clock (26.6 MHz).
Two-wire serial interface data. Connect to V
DD
with 1.5K
resistor even when no other two-wire serial interface
peripheral is attached.
Output in master mode
—
start line sync to drive slave chip
in-phase; input in slave mode.
Output in master mode
—
start frame sync to drive a slave
chip in-phase; input in slave mode.
Asserted when D
OUT
data is valid.
Asserted when D
OUT
data is valid.
Parallel pixel data output 5.
Parallel pixel data output 6.
Parallel pixel data output 7.
Parallel pixel data output 8
Parallel pixel data output 9.
LED strobe output.
Parallel pixel data output 4.
Parallel pixel data output 3.
Parallel pixel data output 2.
Parallel pixel data output 1.
Parallel pixel data output 0.
Pixel clock out. D
OUT
is valid on rising edge of this clock.
Output shift CLK (differential negative).
Output shift CLK (differential positive).
Serial data out (differential negative).
Serial data out (differential positive).
Notes
1
28
30
31
32
33
47
24
OE
S_CTRL_ADR0
S_CTRL_ADR1
RESET#
STANDBY
SYSCLK
S
DATA
Input
Input
Input
Input
Input
Input
I/O
2
22
26
20
21
15
16
17
18
19
27
41
42
43
44
45
46
2
3
4
5
STLN_OUT
STFRM_OUT
LINE_VALID
FRAME_VALID
D
OUT
5
D
OUT
6
D
OUT
7
D
OUT
8
D
OUT
9
LED_OUT
D
OUT
4
D
OUT
3
D
OUT
2
D
OUT
1
D
OUT
0
PIXCLK
SHFT_CLKOUT_N
SHFT_CLKOUT_P
SER_DATAOUT_N
SER_DATAOUT_P
I/O
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
PDF: 09005aef824c9998/Source: 09005aef824c999c
MT9V032_LDS_2.fm - Rev. B 3/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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