PT6311
VFD Driver/Controller IC
DESCRIPTION
PT6311 is a Vacuum Fluorescent Display (VFD)
Controller driven on a 1/8 to 1/16 duty factor housed in
52-pin plastic QFP Package. Twelve segment output
lines, 8 grid output lines, 8 segment/grid output drive
lines, one display memory, control circuit, key scan
circuit are all incorporated into a single chip to build a
highly reliable peripheral device for a single chip micro
computer. Serial data is fed to PT6311 via a three-line
serial interface.
FEATURES
CMOS Technology
Low Power Consumption
Key Scanning (12 x 4 matrix)
Multiple Display Modes: (12 segments, 16 digits to
20 segments, 8 digits)
•
8-Step Dimming Circuitry
•
LED Ports Provide (5 channels, 20mA max.)
•
4- Bits General Purpose Input Ports Provided
•
Serial Interface for Clock, Data Input, Data Output,
Strobe Pins
•
No External Resistors Needed for Driver Outputs
•
Available in 52pins QFP and LQFP
•
•
•
•
APPLICATIONS
•
Microcomputer Peripheral Devices
BLOCK DIAGRAM
Con tro l
DIN
DOUT
CLK
STB
VDD
Ser ial
Data
Inter face
SG 1/KS 1
SG 2/KS 2
SG 3/KS 3
SG 4/KS 4
SG 5/KS 5
SG 6/KS 6
SG 7/KS 7
SG 8/KS 8
SG 9/KS 9
SG 10/KS 10
SG 11 /K S11
SG 12/KS 12
SG 13/G R1 6
SG 14/G R1 5
SG 15/G R1 4
SG 16/G R1 3
SG 17/G R1 2
SG 18/G R11
SG 19/G R1 0
SG 20/G R9
GR1
GR2
GR3
GR4
GR5
GR6
GR7
GR8
Displa y Memo ry
OS C
OS C
Ti ming Ge ner ato r
S egmen t Driver /
G rid Driver /
Ke y Scan O utput
SW1
SW2
SW3
SW4
Ge ner al
Inp ut
Reg iste r
Ke y Matrix Memory
LE D1
LE D2
LE D3
LE D4
LE D5
LED
Drive r
Gr id
Drive r
Dimming Cir cu it
K1 K2 K3 K4
VDD
GND
VE E
Tel: 886-66296288
‧
Fax: 886-29174598
‧
http://www.princeton.com.tw
‧
2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6311
PIN DESCRIPTION
Pin Name
SW1 to SW4
DOUT
I/O
I
O
Description
General Purpose Input Pins
Data Output Pin (N-Channel, Open-Drain)
This pin outputs serial data at the falling edge of the shift
clock (starting from the lower bit).
Data Input Pin
This pin inputs serial data at the rising edge of the shift
clock (starting from the lower bit).
No Connection
Clock Input Pin
This pin reads serial data at the rising edge and outputs
data at the falling edge.
Serial Interface Strobe Pin
The data input after the STB has fallen is processed as a
command. When this in is “HIGH”, CLK is ignored.
Key Data Input Pins
The data inputted to these pins is latched at the end of the
display cycle.
Logic Power Supply
High-Voltage Segment Output Pins
Also acts as the Key Source.
High-Voltage Segment/Grid Output Pins
Pull-Down Level
High-Voltage Grid Output Pins
LED Output Pin
Ground Pin
Oscillator Input Pin
A resistor is connected to this pin to determine the
oscillation frequency.
Pin No.
1 to 4
5
DIN
NC
CLK
I
-
I
6
7
8
STB
I
9
K1 to K4
VDD
SG1/KS1 to SG12/KS12
SG20/GR9 to SG19/GR10
SG18/GR11 to SG13/GR16
VEE
GR1 to GR8
LED1 to LED5
GND
OSC
I
-
O
O
-
O
O
-
I
10 to 13
14, 33, 45
15 to 26
36 to 35
32 to 27
34
44 to 37
50 to 46
51
52
V3.2
4
November 2009
PT6311
INPUT/OUTPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below:
OUTPUT PINS: SGn/GRn
INPUT PINS: DIN, CLK, STB
INPUT PINS: SW1 TO SW4, K1 TO K4
V3.2
5
November 2009
嵌入式系统
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