Preliminary
FM3808
256Kb Bytewide FRAM w/ Real-Time Clock
Features
256K bit Ferroelectric Nonvolatile RAM
•
Organized as 32,752 x 8 bits
•
High Endurance 100 Billion (10
11
) Read/Writes
•
10 year Data Retention
•
NoDelay™ Writes
•
70 ns Access Time/ 130 ns Cycle Time
•
Built-in Low V
DD
Protection
Real-Time Clock/Calendar Function
•
Clock Registers in Top 16 bytes of Address Space
•
Backup Power from External Capacitor or Battery
•
Tracks Seconds through Centuries in BCD Format
•
Tracks Leap Years through 2099
•
Runs from a 32.768 kHz Timekeeping Crystal
System Supervisor Function
•
Programmable Clock/Calendar Alarm
•
Programmable Watchdog Timer
•
Power Supply Monitor
•
Interrupt Output - Programmable active high/low
•
Control Settings Inherently Nonvolatile
•
Generates either Processor Reset or Interrupt
Low Power Operation
•
5V Operation for Memory and Clock Interface
•
Backup Voltage as low as 2.5V
•
25 mA I
DD
Active Current
•
1
µA
I
BAK
Clock Backup Current
Description
The FM3808 combines a 256Kb FRAM array with a
real-time clock and a system supervisor function. An
external 32.768 kHz crystal drives the timekeeping
function. It maintains time and date settings in the
absence of system power through the user’s choice of
backup power source – either a capacitor or a battery.
In either case data in the memory array does not
depend on the backup source, it remains nonvolatile
in FRAM. In addition to timekeeping, the FM3808
includes a system supervisor to manage low V
DD
power conditions and a watchdog timer function. A
programmable interrupt output pin allows the user to
select the supervisor functions and the polarity of the
signal.
Both the FRAM array and the timekeeping function
are accessed through the memory interface. The
upper 16-address locations of the memory space are
allocated to the timekeeping registers rather than to
memory. The FRAM array provides data retention
for 10 years in the absence of system power, and is
not dependent on the backup power source for the
clock. This eliminates system concerns over data loss
in a traditional battery-backed RAM solution. In
addition, clock and supervisor control settings are
implemented in FRAM rather than battery-backed
RAM, making them more dependable. The FM3808
offers guaranteed operation over an industrial
temperature range of -40°C to +85°C.
Pin Configuration
A11
A9
A8
A13
WE
VBAK
INT
VDD
X1
X2
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Ordering Information
FM3808-70-T
70 ns access, 32-pin TSOP
FM3808DK
DIP module development kit
Documentation for the DIP module development kit is
available separately.
This is a product in sampling or pre-production phase of develop-
ment. Characteristic data and other specifications are subject to
change without notice.
Rev 1.1
May 2003
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000, FAX (719) 481-7058
www.ramtron.com
Page 1 of 28
FM3808
Switched
power
System Supervisor
Low VDD monitor/
Watchdog timer
Watchdog
timebase
FRAM Array
32,752x8
VDD
VBAK
INT
Interrupt Control
Logic
Data
Alarm
Address Decoder/
Bus Interface
Address
CE
OE
WE
32.768
kHz
X1
Clock/Calendar
16 Clock/Calendar
Registers
X2
Figure 1. Block Diagram
Pin Description
Pin Name
I/O
A0-A14
Input
DQ(7:0)
/CE
I/O
Input
/OE
/WE
X1, X2
INT
Input
Input
Input
Output
V
BAK
Supply
V
DD
V
SS
Rev 1.1
May 2003
Supply
Supply
Pin Description
Address: The 15 address inputs select one of 32,752 bytes in the FRAM array or one of
16 bytes in the clock/calendar. The address is latched on the falling edge of /CE.
Data: Bi-directional 8-bit data bus for accessing the FRAM array and clock.
Chip Enable: The active low /CE input selects the device. The falling edge of /CE
internally latches the address. Address changes that occur after /CE has transitioned
low are ignored until the next falling edge occurs.
Output Enable: The active low /OE input enables the data output buffers during read
cycles. Deasserting /OE high causes the DQ pins to tri-state.
Write Enable: The active low /WE low enables data on the DQ pins to be written to the
address location latched by the falling edge of /CE.
Connect 32.768 kHz crystal.
Interrupt output: This output can be programmed to respond to the clock/calendar
alarm, the watchdog timer, and the power monitor. It is programmable to either active
high (push/pull) or active low (open-drain).
Backup Supply Voltage: This supply is used to maintain power for the clock. It must
remain between 2.5V and V
DD
-0.3V. V
BAK
is typically supplied by either a capacitor
or a battery. Current is drawn from V
BAK
when V
DD
is below the V
BAK
voltage.
Supply Voltage: 5V
Ground.
Page 2 of 28
FM3808
Functional Truth Table
/CE
/WE
H
X
!
X
L
H
L
L
/OE
X
X
L
X
Function
Standby/Precharge
Latch Address
Read
Write
combined memory map. The register map is
described below, followed by a detailed description
of each functional block.
Overview
The FM3808 integrates three complementary but
distinct functions under a common interface in a
single package. First, is the 32Kx8 FRAM memory
block (minus 16 bytes), second is the real-time
clock/calendar, and third is the system supervisor.
The functions are integrated to enhance their
individual performance, so that each provides better
capability than three similar stand-alone devices. All
functions use the same bytewide address/data
interface and are memory mapped. Special functions,
including the clock/calendar and supervisor system,
are controlled via registers that reside in the top of the
Register Map
The top 16 FRAM address locations control the
clock/calendar, alarm, and supervisor functions. The
registers contain timekeeping data, control bits, or
information flags. A short description of each register
follows. Detailed descriptions of each function follow
the register summary.
Register Map Summary Table
Data
Address
7FFFh
7FFEh
7FFDh
7FFCh
7FFBh
7FFAh
7FF9h
7FF8h
7FF7h
7FF6h
7FF5h
7FF4h
7FF3h
7FF2h
7FF1h
7FF0h
D6
D5
D4
10 years
0
0
0
10 mo
0
0
10 date
0
0
0
0
0
0
10 hours
0
10 minutes
0
10 seconds
/OSCEN reserved reserved
CALS
WDS
/WDW
WDT5
WDT4
WIE
AIE
PFE
ABE
/Match
0
Alarm 10 date
/Match
0
Alarm 10 hours
/Match
Alarm 10 minutes
/Match
Alarm 10 seconds
WDF
AF
PF
CF
D7
D3
D1
D0
Function
years
Years
months
Month
date
Date
day
Day
hours
Hours
minutes
Minutes
seconds
Seconds
CAL2
CAL1
CAL0 Control-NV
WDT2
WDT1
WDT0 Watchdog
P/L
reserved reserved Interrupts
Alarm date
Alarm Date
hours
Alarm Hours
Alarm minutes
Alarm Minutes
Alarm seconds
Alarm Seconds
User-NV
CAL
W
R
Flags/Control
D2
Range
00-99
1-12
1-31
1-7
0-23
0-59
0-59
0
CAL3
WDT3
H/L
1-31
0-23
0-59
0-59
TST
Note that the shaded register bits are implemented in FRAM, therefore data at these locations is retained even
without backup power.
Rev 1.1
May 2003
Page 3 of 28
FM3808
Table 1. Register Map
Address
7FFFh
Description
Timekeeping – Years
D7
10 year.3
D6
10 year.2
D5
10 year.1
D4
10 year.0
D3
Year.3
D2
Year.2
D1
Year.1
D0
Year.0
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble
contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99.
7FFEh
Timekeeping – Months
D7
0
D6
0
D5
0
D4
10 Month
D3
Month.3
D2
Month.2
D1
Month.1
D0
Month.0
Contains the BCD digits for the month. Lower nibble contains the lower digit and operates from 0 to 9;
upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-
12.
7FFDh
Timekeeping – Date of the month
D7
0
D6
0
D5
10 date.1
D4
10 date.0
D3
Date.3
D2
Date.2
D1
Date.1
D0
Date.0
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates
from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for the register is
1-31.
7FFCh
Timekeeping – Day of the week
D7
0
D6
0
D5
0
D4
0
D3
0
D2
Day.2
D1
Day.1
D0
Day.0
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that
counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not
integrated with the date.
7FFBh
Timekeeping – Hours
D7
0
D6
0
D5
10 hours.1
D4
10 hours.0
D3
Hours.3
D2
Hours2
D1
Hours.1
D0
Hours.0
Contains the BCD value of hours in 24-hour format. Lower nibble contains the lower digit and operates
from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the
register is 0-23.
7FFAh
Timekeeping – Minutes
D7
0
D6
10 min.2
D5
10 min.1
D4
10 min.0
D3
Min.3
D2
Min.2
D1
Min.1
D0
Min.0
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9;
upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59.
7FF9h
Timekeeping – Seconds
D7
0
D6
10 sec.2
D5
10 sec.1
D4
10 sec.0
D3
Seconds.3
D2
Seconds.2
D1
Seconds.1
D0
Seconds.0
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9;
upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 0-59.
Rev 1.1
May 2003
Page 4 of 28
FM3808
Address
7FF8h
Description
Control-Nonvolatile
D7
OSCEN
D6
Reserved
D5
Reserved
D4
CALS
D3
CAL.3
D2
CAL.2
D1
CAL.1
D0
CAL.0
/OSCEN
Reserved
CALS
CAL.3-0
/Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling
the oscillator saves battery power during storage. On a no-battery power up, this bit is set to 1.
The
RTC will not run until the oscillator is enabled. Set this bit to 0 to activate the RTC.
Do not use. Should remain set to 0.
Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction
from the time-base. This bit is implemented in FRAM. Calibration is explained below
These four bits control the calibration of the clock. These bits are implemented in FRAM.
7FF7h
Watchdog Timer
D7
WDS
D6
WDW
D5
WDT.5
D4
WDT.4
D3
WDT.3
D2
WDT.2
D1
WDT.1
D0
WDT.0
WDS
/WDW
WDT.5-0
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no
affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is write only.
Reading it always will return a 0.
Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT.5-0) so it cannot
be written. This allows the user to strobe the watchdog without disturbing the timeout value. Setting this
bit to 0 allows bits 5-0 to be written on the next write to the Watchdog register. The new value will be
loaded on the next internal watchdog clock after the write cycle is complete. This function is explained
in more detail in the watchdog Timer section below.
Watchdog Timeout selection. The watchdog timer interval is selected by the 6-bit value in this register.
It represents a multiplier of the 32 Hz count (31.25 ms). The minimum range or timeout value is 31.25
ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3Fh). Setting the watchdog timer
register to 0 disables the timer. These bits can be written only if the /WDW bit was cleared to 0 on a
previous cycle.
7FF6h
Interrupts
D7
WIE
D6
AIE
D5
PFE
D4
ABE
D3
H/L
D2
P/L
D1
Reserved
D0
Reserved
WIE
AIE
PFE
ABE
H/L
P/L
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives
the INT pin as well as the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When
set to 0, the alarm match only affects the AF flag.
Power-Fail Enable. When set to 1, the power-fail monitor drives the pin as well as the PF flag. When set
to 0, the power-fail monitor affects only the PF flag.
Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function
even in battery backup mode. When set to 0, the alarm will occur only when VDD>VLO.
High/Low. When set to a 1, the INT pin is push/pull active high. When set to a 0, the INT pin is open
drain, active low.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source
for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until
the Flags/Control register is read.
7FF5h
Alarm – Date of the month
D7
M
D6
0
D5
10 date.1
D4
10 date.0
D3
Date.3
D2
Date.2
D1
Date.1
D0
Date.0
/M
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the date value.
Rev 1.1
May 2003
Page 5 of 28
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