Pre-Production
FM4005
Integrated Processor Companion
Features
High Integration Device Replaces Multiple Parts
•
Real-time Clock (RTC)
•
Low Voltage Reset
•
Watchdog Timer
•
Early Power-Fail Warning/NMI
•
Two 16-bit Event Counters
•
Serial Number with Write-lock for Security
Real-Time Clock/Calendar
•
Backup Current under 1
µA
•
Seconds through Centuries in BCD format
•
Tracks Leap Years through 2099
•
Uses Standard 32.768 kHz Crystal (6pF)
•
Software Calibration
•
Calibration Data is Nonvolatile
•
Programmed Settings are Nonvolatile
•
Supports Battery or Capacitor Backup
Processor Companion
•
Active-low Reset Output for V
DD
and Watchdog
•
Programmable Low V
DD
Reset Thresholds
•
Manual Reset Filtered and Debounced
•
Programmable Watchdog Timer
•
Dual Battery-backed Event Counter Tracks System
Intrusions or other Events
•
Comparator for Early Power-Fail Interrupt
•
64-bit Programmable Serial Number with Lock
Fast Two-wire Serial Interface
•
Up to 1 MHz Maximum Bus Frequency
•
Supports Legacy Timing for 100 kHz & 400 kHz
Easy to Use Configurations
•
Operates from 2.7 to 5.5V
•
Small Footprint 14-pin “Green” SOIC (-G)
•
Low Operating Current
•
-40°C to +85°C Operation
The processor companion includes commonly needed
CPU support functions. Supervisory functions
include a reset output signal controlled by either a
low VDD condition or a watchdog timeout. /RST
goes active when VDD drops below a programmable
threshold and remains active for 100 ms after VDD
rises above the trip point. A programmable watchdog
timer runs from 100 ms to 3 seconds. The watchdog
timer is optional, but if enabled it will assert the reset
signal for 100 ms if not restarted by the host before
the timeout. A flag-bit indicates the source of the
reset.
A general-purpose comparator compares an external
input pin to the onboard 1.2V reference. This is
useful for generating a power-fail interrupt (NMI) but
can be used for any purpose. The device also includes
a programmable 64-bit serial number that can be
locked making it unalterable. Additionally it offers a
dual battery-backed event counter that tracks the
number of rising or falling edges detected on
dedicated input pins.
Description
The FM4005 is an integrated device that includes the
most commonly needed functions for processor-
based systems. Major features include real-time
clock, low-V
DD
reset, watchdog timer, battery-backed
event counter, lockable 64-bit serial number area, and
general purpose comparator that can be used for a
power-fail (NMI) interrupt or other purpose. The
family operates from 2.7 to 5.5V.
The real-time clock (RTC) provides time and date
information in BCD format. It can be permanently
powered from external backup voltage source, either
a battery or a capacitor. The timekeeper uses a
common external 32.768 kHz crystal and provides a
calibration mode that allows software adjustment of
timekeeping accuracy.
This is a product in pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change
the specifications. Ramtron will issue a Product Change Notice if
any specification changes are made.
Rev. 2.3
Oct. 2006
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 23
FM4005
Pin Configuration
CNT1
CNT2
DNU
DNU
CAL/PFO
RST
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
SCL
SDA
X2
X1
PFI
VBAK
Pin Name
CNT1, CNT2
CAL/PFO
/RST
PFI
X1, X2
SDA
SCL
DNU
VBAK
VDD
VSS
Function
Battery-backed Counter Inputs
Clock Calibration and Early
Power-fail Output
Reset Input/Output
Early Power-fail Input
Crystal Connections
Serial Data
Serial Clock
Do Not Use
Battery-Backup Supply
Supply Voltage
Ground
Ordering Information
Base Configuration
FM4005
Operating Voltage
2.7-5.5V
Reset Threshold
2.6V, 2.9, 3.9, 4.4V
Ordering Part Number
FM4005-G
Rev. 2.3
Oct. 2006
Page 2 of 23
FM4005
SCL
SDA
2-Wire
Interface
LockOut
RST
Watchdog
LV Detect
Special
Function
Registers
S/N
RTC Cal.
RTC Registers
X1
PFI
+
CAL/PFO
RTC
1.2V
X2
-
-
+
512Hz
Event
Counters
CNT1
CNT2
2.5V
VDD
Switched Power
VBAK
Nonvolatile
Battery Backed
Figure 1. Block Diagram
Pin Descriptions
Pin Name
CNT1, CNT2
Type
Input
Pin Description
Event Counter Inputs: These battery-backed inputs increment counters when an edge is
detected on the corresponding CNT pin. The polarity is programmable. These pins
should not be left floating. Tie to ground if pins are not used.
In calibration mode, this pin supplies a 512 Hz square-wave output for clock
calibration. In normal operation, this is the early power-fail output.
32.768 kHz crystal connection. When using an external oscillator, apply the clock to
X1 and leave X2 floating.
Active low reset output with weak pull-up. Also input for manual reset.
Serial Data & Address: This is a bi-directional line for the two-wire interface. It is
open-drain and is intended to be wire-OR’d with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. A pull-up resistor is required.
Serial Clock: The serial clock line for the two-wire interface. Data is clocked out of the
part on the falling edge, and in on the rising edge. The SCL input also incorporates a
Schmitt trigger input for noise immunity.
Early Power-fail Input: Typically connected to an unregulated power supply to detect
an early power failure. This pin should not be left floating.
Do Not Use: This pin must be left floating.
Backup supply voltage: A 3V battery or a large value capacitor. If V
DD
<3.6V and no
backup supply is used, this pin should be tied to V
DD
. If V
DD
>3.6V and no backup
supply is used, this pin should be left floating and the VBC bit should be set.
Supply Voltage.
Ground
CAL/PFO
X1, X2
/RST
SDA
Output
I/O
I/O
I/O
SCL
Input
PFI
DNU
VBAK
Input
-
Supply
VDD
VSS
Supply
Supply
Rev. 2.3
Oct. 2006
Page 3 of 23
FM4005
Overview
The FM4005 combines a real-time clock (RTC) and a
processor companion. The companion is a highly
integrated peripheral that includes a processor
supervisor, a comparator used for early power-fail
warning, nonvolatile event counters, and a 64-bit
serial number. The FM4005 integrates these
functions that share a common interface in a single
package.
The real-time clock and supervisor functions are
accessed with a standard 2-wire device ID. The clock
and supervisor functions are controlled by 25 special
function registers. Some of these functions such as
the RTC and event counter circuits are maintained by
the power source on the VBAK pin, allowing them to
operate from battery or backup capacitor power when
V
DD
drops below an internally set threshold. Each
functional block is described below.
VDD
VTP
tRPU
RST
Figure 2. Low VDD Reset
The watchdog timer can also be used to assert the
reset signal (/RST). The watchdog is a free running
programmable timer. The period can be software
programmed from 100 ms to 3 seconds in 100 ms
increments via a 5-bit nonvolatile register. All
programmed settings are minimum values and vary
with temperature according to the operating
specifications. The watchdog has two additional
controls associated with its operation, a watchdog
enable bit (WDE) and timer restart bits (WR). Both
the enable bit must be set and the watchdog must
timeout in order to drive /RST active. If a reset event
occurs, the timer will automatically restart on the
rising edge of the reset pulse. If not enabled, the
watchdog timer runs but has no effect on /RST. Note
that setting the maximum timeout setting (11111b)
disables the counter to save power. The second
control is a nibble that restarts the timer preventing a
reset. The timer should be restarted after changing the
timeout value.
The watchdog timeout value is located in register
0Ah, bits 4-0, the watchdog enable is bit 7. The
watchdog is restarted by writing the pattern 1010b to
the lower nibble of register 09h. Writing this pattern
will also cause the timer to load new timeout values.
Writing other patterns to this address will not affect
its operation. Note the watchdog timer is free-
running. Prior to enabling it, users should restart the
timer as described above. This assures that the full
timeout period will be set immediately after enabling.
The watchdog is disabled when VDD is below VTP.
The following table summarizes the watchdog bits. A
block diagram follows.
Watchdog timeout
Watchdog enable
Watchdog restart
100 ms
clock
Timebase
Processor Supervisor
Supervisors provide a host processor two basic
functions: detection of power supply fault conditions
and a watchdog timer to escape a software lockup
condition. The FM4005 has a reset pin (/RST) to
drive the processor reset input during power faults
(and power-up) and software lockups. It is an open
drain output with a weak internal pull-up to V
DD
.
This allows other reset sources to be wire-OR’d to
the /RST pin. When V
DD
is above the programmed
trip point, /RST output is pulled weakly to V
DD
. If
V
DD
drops below the reset trip point voltage level
(V
TP
) the /RST pin will be driven low. It will remain
low until V
DD
falls too low for circuit operation
which is the V
RST
level. When V
DD
rises again above
V
TP
, /RST will continue to drive low for at least 100
ms (t
RPU
) to ensure a robust system reset at a reliable
V
DD
level. After t
RPU
has been met, the /RST pin will
return to the weak high state. While /RST is asserted,
serial bus activity is locked out even if a transaction
occurred as V
DD
dropped below V
TP
. Any register
read or write operation started while V
DD
is above
V
TP
will be completed internally.
The bits VTP1 and VTP0 control the trip point of the
low voltage detect circuit. They are located in register
0Bh, bits 1 and 0. Figure 2 illustrates the reset
operation in response to the V
DD
voltage.
VTP
2.6V
2.9V
3.9V
4.4V
VTP1
0
0
1
1
VTP0
0
1
0
1
WDT4.0
WDE
WR3-0
0Ah, D4-0
0Ah, D7
09h, D3-0
WR3-0 = 1010b
Down Counter
Watchdog
timeout
/RST
WDE
Figure 3. Watchdog Timer
Rev. 2.3
Oct. 2006
Page 4 of 23
FM4005
Manual Reset
The /RST pin is bi-directional and allows the
FM4005 to filter and de-bounce a manual reset
switch. The /RST input detects an external low
condition and responds by driving the /RST signal
low for 100 ms. Note that an internal weak pull-up on
/RST eliminates the need for additional external
components.
MCU
RST
Reset
Switch
Regulator
VDD
FM4005
FM4005
To MCU CAL/PFO
NMI input
+
-
1.2V ref
Switch
Behavior
Figure 5. Comparator as a Power-fail Warning
FM4005
drives
100 ms
RST
The comparator is a general purpose device and its
application is not limited to the NMI function.
The comparator is not integrated into the special
function registers except as it shares its output pin
with the CAL output. When the RTC calibration
mode is invoked by setting the CAL bit (register 00h,
bit 2), the CAL/PFO output pin will be driven with a
512 Hz square wave and the comparator will be
ignored. Since most users only invoke the calibration
mode during production, this should have no impact
on system operations using the comparator.
Note: The maximum voltage on the comparator input PFI
is limited to 3.75V under normal operating conditions.
Figure 4. Manual Reset
Reset Flags
In case of a reset condition, a flag will be set to
indicate the source of the reset. A low V
DD
reset or
manual reset is indicated by the POR flag, register
09h bit 6. A watchdog reset is indicated by the WTR
flag, register 09h bit 7. Note that the bits are
internally set in response to reset sources, but they
must be cleared by the user. When the register is
read, it is possible that both flags are set if both have
occurred since the user last cleared them.
Early Power Fail Comparator
An early power fail warning can be provided to the
processor well before V
DD
drops out of spec. The
comparator is used to create a power fail interrupt
(NMI). This can be accomplished by connecting the
PFI pin to the unregulated power supply via a resistor
divider. An application circuit is shown below. The
voltage on the PFI input pin is compared to an
onboard 1.2V reference. When the PFI input voltage
drops below this threshold, the comparator will drive
the CAL/PFO pin to a low state. The comparator has
350 mV (max) of hysteresis to reduce noise
sensitivity, only for a rising PFI signal. For a falling
PFI edge, there is no hysteresis.
Event Counter
The FM4005 offers the user two battery-backed event
counters. The input pins CNT1 and CNT2 are
programmable edge detectors. Each controls a 16-bit
counter. When an edge occurs, the counters will
increment their respective registers. Counter 1 is
located in registers 0Dh and 0Eh. Counter 2 is
located in registers 0Fh and 10h. These register
values can be read anytime VDD is above VTP, and
they will be incremented as long as a valid VBAK
power source is provided. To read, set the RC bit
register 0Ch bit 3 to 1. This takes a snapshot of all
four counter bytes allowing a stable value even if a
count occurs during the read. The registers can be
written by software allowing the counters to be
cleared or initialized by the system. Counts are
blocked during a write operation. The two counters
can be cascaded to create a single 32-bit counter by
setting the CC control bit (register 0Ch). When
cascaded, the CNT1 input will cause the counter to
increment. CNT2 is not used in this mode.
The control bits for event counting are located in
register 0Ch. Counter 1 Polarity is bit C1P, bit 0;
Rev. 2.3
Oct. 2006
Page 5 of 23
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