Preliminary
FM28V100
1Mbit Bytewide F-RAM Memory
Features
1Mbit Ferroelectric Nonvolatile RAM
•
Organized as 128Kx8
•
High Endurance 100 Trillion (10
14
) Read/Writes
•
NoDelay™ Writes
•
Page Mode Operation to 33MHz
•
Advanced High-Reliability Ferroelectric Process
Superior to Battery-backed SRAM Modules
•
No battery concerns
•
Monolithic reliability
•
True surface mount solution, no rework steps
•
Superior for moisture, shock, and vibration
SRAM Replacement
•
JEDEC 128Kx8 SRAM pinout
•
60 ns Access Time, 90 ns Cycle Time
Low Power Operation
•
2.0V – 3.6V Power Supply
•
Standby Current 90
µA
(typ)
•
Active Current 7 mA (typ)
Industry Standard Configurations
•
Industrial Temperature -40° C to +85° C
•
32-pin “Green”/RoHS Package
General Description
The FM28V100 is a 128K x 8 nonvolatile memory
that reads and writes like a standard SRAM. A
ferroelectric random access memory or F-RAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and very high write endurance make
F-RAM superior to other types of memory.
In-system operation of the FM28V100 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by toggling a chip enable pin
or simply by changing the address. The F-RAM
memory is nonvolatile due to its unique ferroelectric
memory process. These features make the FM28V100
ideal for nonvolatile memory applications requiring
frequent or rapid writes in the form of an SRAM.
Device specifications are guaranteed over the
industrial temperature range -40°C to +85°C.
Pin Configuration
A11
A9
A8
A13
WE
CE2
A15
VDD
NC*
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
TSOP-I
* Reserved for A17 on 2Mb
Ordering Information
FM28V100-TG
32-pin “Green”/RoHS TSOP
FM28V100-TGTR 32-pin “Green”/RoHS TSOP,
Tape & Reel
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.1
Mar. 2009
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 13
FM28V100 - 128Kx8 FRAM
Overview
The FM28V100 is a bytewide F-RAM memory
logically organized as 131,072 x 8 and is accessed
using an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page is triggered
by toggling a chip enable pin or simply by changing
the upper address A(16:3).
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when the device is activated with a chip enable.
In this case, the device begins the memory cycle as a
write. The FM28V100 will not drive the data bus
regardless of the state of /OE as long as /WE is low.
Input data must be valid when the device is
deselected with a chip enable. In a /WE-controlled
write, the memory cycle begins when the device is
activated with a chip enable. The /WE signal falls
some time later. Therefore, the memory cycle begins
as a read. The data bus will be driven if /OE is low,
however it will hi-Z once /WE is asserted low. The
/CE- and /WE-controlled write timing cases are
shown on page 12. In the
Write Cycle Timing 2
diagram, the data bus is shown as a hi-Z condition
while the chip is write-enabled and before the
required setup time. Although this is drawn to look
like a mid-level voltage, it is recommended that all
DQ pins comply with the minimum V
IH
/V
IL
operating
levels.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the deassertion of /WE, /CE1, or
CE2, whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to deasserting /WE, /CE1, or CE2. Data setup
time indicates the interval during which data cannot
change prior to the end of the write access.
Unlike other truly nonvolatile memory technologies,
there is no write delay with F-RAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Data polling, a technique used with
EEPROMs to determine if a write is complete, is
unnecessary.
Page Mode Operation
The FM28V100 provides the user fast access to any
data within a row element. Each row has eight
column locations (bytes). An access can start
anywhere within a row and other column locations
may be accessed without the need to toggle the CE
pins. For page mode reads, once the first data byte is
driven onto the bus, the column address inputs A(2:0)
may be changed to a new value. A new data byte is
then driven to the DQ pins. For page mode writes,
the first write pulse defines the first write access.
While the device is selected (both chip enables
asserted), a subsequent write pulse along with a new
column address provides a page mode write access.
Memory Operation
Users access 131,072 memory locations with 8 data
bits each through a parallel interface. The F-RAM
array is organized as 16,384 rows and each row has 8
column locations (bytes), which allows fast access in
page mode operation. Once an initial address has
been latched by the falling edge of /CE1 (while CE2
high) or the rising edge of CE2 (while /CE1 low),
subsequent column locations may be accessed
without the need to toggle a chip enable. When either
chip enable pin is deasserted, a precharge operation
begins. Writes occur immediately at the end of the
access with no delay. The /WE pin must be toggled
for each write operation.
Read Operation
A read operation begins on the falling edge of /CE1
(while CE2 high) or the rising edge of CE2 (while
/CE1 low). The /CE-initiated access causes the
address to be latched and starts a memory read cycle
if /WE is high. Data becomes available on the bus
after the access time has been satisfied. Once the
address has been latched and the access completed, a
new access to a random location (different row) may
begin while both chip enables are still active. The
minimum cycle time for random addresses is t
RC
.
Note that unlike SRAMs, the FM28V100’s /CE-
initiated access time is faster than the address cycle
time.
The FM28V100 will drive the data bus only when
/OE is asserted low and the memory access time has
been satisfied. If /OE is asserted prior to completion
of the memory access, the data bus will not be driven
until valid data is available. This feature minimizes
supply current in the system by eliminating transients
caused by invalid data being driven onto the bus.
When /OE is inactive, the data bus will remain hi-Z.
Write Operation
Writes occur in the FM28V100 in the same time
interval as reads. The FM28V100 supports both /CE-
and /WE-controlled write cycles. In both cases, the
address is latched on the falling edge of /CE1 (while
CE2 high) or the rising edge of CE2 (while /CE1
low).
Rev. 1.1
Mar. 2009
Page 4 of 13
FM28V100 - 128Kx8 FRAM
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is prepared for a new
access. Precharge is user-initiated by driving at least
one of the chip enable signals to an inactive state. The
chip enable must remain inactive for at least the
minimum precharge time t
PC
.
Endurance
The FM28V100 is capable of being accessed at least
10
14
times – reads or writes. An F-RAM memory
operates with a read and restore mechanism.
Therefore, an endurance cycle is applied on a row
basis. The F-RAM architecture is based on an array
of rows and columns. Rows are defined by A16-A3
and column addresses by A2-A0. The array is
organized as 16K rows of 8-bytes each. The entire
row is internally accessed once whether a single byte
or all eight bytes are read or written. Each byte in the
row is counted only once in an endurance calculation.
The user may choose to write CPU instructions and
run them from a certain address space. The table
below shows endurance calculations for 256-byte
repeating loop, which includes a starting address, 7
page mode accesses, and a CE precharge. The
number of bus clocks needed to complete an 8-byte
transaction is 8+1 at lower bus speeds, but 9+2 at
33MHz due to initial read latency and an extra clock
to satisfy the device’s precharge timing constraint t
PC
.
The entire loop causes each byte to experience only
one endurance cycle.
F-RAM read and write
endurance is virtually unlimited even at 33MHz
system bus clock rate.
Table 1. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop
Bus Freq Bus Cycle
256-byte
Endurance
Endurance
Years to
(MHz)
Time (ns) Transaction Cycles/sec.
Cycles/year
Reach 10
14
Cycles
Time (µs)
µ
12
30
10.56
33
94,690
2.98 x 10
33.5
12
40
12.8
40.6
25
78,125
2.46 x 10
12
10
100
28.8
34,720
1.09 x 10
91.7
11
5
200
57.6
17,360
5.47 x 10
182.8
Rev. 1.1
Mar. 2009
Page 5 of 13
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