Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
Electronic Volume Controller IC
PT2257
DESCRIPTION
PT2257 is an Electronic Volume Controller IC utilizing CMOS Technology specially designed for the
new generation of AV entertainment products. It has two (2) built-in channels making it ideally suitable
for mono and stereo sound applications. PT2257 provides an I
2
C Control Interface, an attenuation
range of 0 to -79dB, low noise, and high channel separation. It is housed in an 8 pins, DIP or SOP
Package, PT2257’s pin assignments and application circuit are optimized for easy PCB layout and cost
saving advantages.
FEATURES
•
•
•
•
•
•
•
•
CMOS Technology
Low Power Consumption
Least External Components
Attenuation Range: 0 to -79dB at 1dB/step
Operating Voltage: 4 to 9V
Low Noise, S/N Ratio>100dB (A-weighting)
Two Channel Output
Available in 8 pins, DIP or SOP
APPLICATIONS
•
•
•
•
•
AV Surround Audio Equipment
Car Audio
Mini Compo
Computer Multi-Media Speaker
Other Audio Equipment
PT2257 V1.3
-1-
December, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
Electronic Volume Controller IC
PT2257
BLOCK DIAGRAM
V
DD
L
IN
1 0 d B /S t e p
1 d B /S te p
+
-
+
-
R ef
L
O UT
1 0 d B /S t e p
-
+
1 d B /S te p
R
OU T
R
IN
C ontrol unit
S DA
S CL
V ss
PT2257 V1.3
-2-
December, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
Electronic Volume Controller IC
PT2257
PIN CONFIGURATION
LIN
LOUT
VS S
SDA
PT 2257
RIN
ROUT
VDD
SCL
PIN DESCRIPTION
Pin Name
L
IN
L
OUT
V
SS
SDA
SCL
V
DD
R
OUT
R
IN
I/O
I
O
-
I
I
-
O
I
Description
Left Input Channel
Connect a Capacitor to Audio Source
Left Output Channel
Connect a Capacitor to Audio Output
Ground
I
2
C Data Input
I
2
C Clock Input
Power Supply
Right Output Channel
Connect a Capacitor to Audio Output
Right Input Channel
Connect a Capacitor to Audio Source
Pin No.
1
2
3
4
5
6
7
8
PT2257 V1.3
-3-
December, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
Electronic Volume Controller IC
PT2257
FUNCTION DESCRIPTION
BUS INTERFACE
Data are transmitted to and from the microprocessor to the PT2257 via the SDA and SCL. The SDA
and SCL make up the BUS Interface. It should be noted that the pull-up resistors must be connected to
the positive supply voltage.
DATA VALIDITY
A data on the SDA Line is considered valid and stable only when the SCL Signal is in HIGH State. The
HIGH and LOW States of the SDA Line can only change when the SCL signal is LOW. Please refer to
the figure below.
D ATA
CLK
D a t a Lin e
S ta b le ,
D a t a Va lid
D a ta
C h a ng e
A llo w e d
START AND STOP CONDITIONS
A Start Condition is activated when
1. the SCL is set to HIGH and
2. SDA shifts from HIGH to LOW State.
The Stop Condition is activated when
1. SCL is set to HIGH and
2. SDA shifts from LOW to HIGH State.
Please refer to the timing diagram below.
CLK
DATA
Start
Stop
PT2257 V1.3
-4-
December, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
Electronic Volume Controller IC
PT2257
BYTE FORMAT
Every byte transmitted to the SDA Line consists of 8 bits. Each byte must be followed by an
Acknowledge Bit. The MSB is transmitted first.
ACKNOWLEDGE
During the Acknowledge Clock Pulse, the master (µP) puts a resistive HIGH level on the SDA Line.
The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during the
Acknowledge Clock Pulse so that the SDA Line is in a Stable Low State during this Clock Pulse. Please
refer to the diagram below.
SC L
1
2
3
4
7
8
9
SD A
Start
MSB
A cknowledgment
from R eceiver
The audio processor that has been addressed has to generate an Acknowledge after receiving each
byte; otherwise, the SDA Line will remain at the High Level during the ninth (9th) Clock Pulse. In this
case, the master transmitter can generate the STOP Information in order to abort the transfer.
TRANSMISSION WITHOUT ACKNOWLEDGE
If you want to avoid the acknowledge detection of the audio processor, a simpler µP transmission may
be used. Wait one clock and do not check the slave acknowledge of this same clock then send the new
data. If you use this approach, there are greater chances of faulty operation as well as decrease in
noise immunity.
PT2257 V1.3
-5-
December, 2006
FPGA/CPLD
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