Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer
(16
×
64
×
8)
PLUS405-55
DESCRIPTION
The PLUS405-55 device is a bipolar,
programmable state machine of the Mealy
type. Both the AND and the OR array are
user-programmable. All 64 AND gates are
connected to the 16 external dedicated inputs
(I0 - I15) and to the feedback paths of the
8 on-chip State Registers (Q
P0
- Q
P7
). Two
complement arrays support complex
IF-THEN-ELSE state transitions with a single
product term (input variables C
0
, C
1).
All state transition terms can include True,
False and Don’t Care states of the controlling
state variables. All AND gates are merged
into the programmable OR array to issue the
next-state and next-output commands to their
respective registers. Because the OR array is
programmable, any one or all of the 64
transition terms can be connected to any or
all of the State and Output Registers.
All state (Q
P0
- Q
P7
) and output (Q
F0
- Q
F7
)
registers are edge-triggered, clocked J-K
flip-flops, with Asynchronous Preset and
Reset options. The PLUS405 architecture
provides the added flexibility of the J-K toggle
function which is indeterminate on S-R
flip-flops. Each register may be individually
programmed such that a specific
Preset-Reset pattern is initialized when the
initialization pin is raised to a logic level “1”.
This feature allows the state machine to be
asynchronously initialized to known internal
state and output conditions prior to
proceeding through a sequence of state
transitions. Upon power-up, all registers are
unconditionally preset to “1”. If desired, the
initialization input pin (INIT) can be converted
to an Output Enable (OE) function as an
additional user-programmable feature.
Availability of two user-programmable clocks
allows the user to design two independently
clocked state machine functions consisting of
four state and four output bits each.
Order codes are listed in the Ordering
Information Table below.
FEATURES
•
66.7MHz minimum guaranteed clock rate
•
55MHz minimum guaranteed operating
•
Functional superset of PLS105/105A
•
Field-programmable (Ti-W fusible link)
•
16 input variables
•
8 output functions
•
64 transition terms
•
8-bit State Register
•
8-bit Output Register
•
2 transition Complement Arrays
•
Multiple clocks
•
Programmable Asynchronous Initialization
•
Power-on preset of all registers to “1”
•
“On-chip” diagnostic test mode features for
•
950mW power dissipation (typ.)
•
TTL compatible
•
J-K or S-R flip-flop functions
•
Automatic “Hold” states
•
3-State outputs
APPLICATIONS
access to state and output registers
or Output Enable
frequency (1/(t
IS1
+ t
CKO1
)
PIN CONFIGURATIONS
N Package
CLK 1
I7 2
I6 3
I5/CLK 4
I4 5
I3 6
I2 7
I1 8
I0 9
F7 10
F6 11
F5 12
F4 13
GND 14
28 V
CC
27 I8
26 I9
25 I10
24 I11
23 I12
22 I13
21 I14
20 I15
19 INIT/OE
18 F0
17 F1
16 F2
15 F3
N = Plastic DIP (600mil-wide)
A Package
I5/CLK I6
4
I4 5
I3 6
I2 7
I1 8
I0 9
F7 10
F6 11
12
13
14
15
16
17
18
3
I7 CLK V
CC
I8
1 28 27
2
I9
26
25 I10
24 I11
23 I12
22 I13
21 I14
20 I15
19 INIT/OE
•
Interface protocols
•
Sequence detectors
•
Peripheral controllers
•
Timing generators
•
Sequential circuits
•
Elevator contollers
•
Security locking systems
•
Counters
•
Shift registers
F5 F4 GND F3 F2 F1 F0
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
28-Pin Plastic Dual In-Line (600mil-wide)
28-Pin Plastic Leaded Chip Carrier
OPERATING
FREQUENCY
55MHz (t
IS
+ t
CKO
)
55MHz (t
IS
+ t
CKO
)
ORDER CODE
PLUS405–55N
PLUS405–55A
DRAWING NUMBER
0413B
0401F
October 22, 1993
180
853–1546 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer
(16
×
64
×
8)
PLUS405-55
PIN DESCRIPTION
PIN NO.
1
SYMBOL
CLK1
NAME AND FUNCTION
Clock:
The Clock input to the State and Output Registers. A Low-to-High transition on this
line is necessary to update the contents of both state and output registers. Pin 1 only
clocks P0–3 and F0–3 if Pin 4 is also being used as a clock.
Logic Inputs:
The 12 external inputs to the AND array used to program jump conditions
between machine states, as determined by a given logic sequence. True and complement
signals are generated via use of “H” and “L”.
Logic Input/Clock:
A user programmable function:
POLARITY
Active-High (H)
2, 3, 5–9,
26–27
20–22
4
I0 – I4, I7, I6
I8 – I9
I13 – I15
CLK2
Active-High/Low
(H/L)
•
Logic Input:
A 13th external logic input to the AND array, as above.
•
Clock:
A 2nd clock for the State Registers P4–7 and Output Registers F4–7, as above.
Note that input buffer I5 must be deleted from the AND array (i.e., all fuse locations “Don’t
Care”) when using Pin 4 as a Clock.
23
I12
Logic/Diagnostic Input:
A 14th external logic input to the AND array, as above, when
exercising standard TTL or CMOS levels. When I12 is held at +10V, device outputs F0–F7
reflect the contents of State Register bits P0–P7. The contents of each Output Register
remains unaltered.
Logic/Diagnostic Input:
A 15th external logic input to the AND array, as above, when
exercising standard TTL levels. When I11 is held at +10V, device outputs F0–F7 become
direct inputs for State Register bits P0–P7; a Low-to-High transition on the appropriate
clock line loads the values on pins F0–F7 into the State Register bits P0–P7. The contents
of each Output Register remains unaltered.
Logic/Diagnostic Input:
A 16th external logic input to the AND array, as above, when
exercising standard TTL levels. When I10 is held at +10V, device outputs F0–F7 become
direct inputs for Output Register bits Q0–Q7; a Low-to-High transition on the appropriate
clock line loads the values on pins F0–F7 into the Output Register bits Q0–Q7. The
contents of each State Register remains unaltered.
Logic Outputs/Diagnostic Outputs/Diagnostic Inputs:
Eight device outputs which
normally reflect the contents of Output Register Bits Q0–Q7, when enabled. When I12 is
held at +10V, F0–F7 = (P0–P7). When I11 is held at +10V, F0–F7 become inputs to State
Register bits P0–P7. When I10 is held at +10V, F0–F7 become inputs to Output Register
bits Q0–Q7.
Initialization or Output Enable Input:
A user programmable function:
Active-High/Low
(H/L)
Active-High (H)
Active-High/Low
(H/L)
24
I11
Active-High/Low
(H/L)
25
I10
Active-High/Low
(H/L)
10–13
15–18
F0 – F7
Active-High (H)
19
INIT/OE
•
Initialization:
Provides an asynchronous preset to logic “1” or reset to logic “0” of all
State and Output Register bits, determined individually for each register bit through user
programming. INIT overrides Clock, and when held High, clocking is inhibited and F0–F7
and P0–P7 are in their initialization state. Normal clocking resumes with the first full clock
pulse following a High-to-Low clock transition, after INIT goes Low. See timing definition for
t
NVCK
and t
VCK
.
Active-High (H)
•
Output Enable:
Provides an output enable function to buffers F0–F7 from the Output
Registers.
Active-Low (L)
October 22, 1993
181
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer
(16
×
64
×
8)
TRUTH TABLE
1, 2, 3, 4, 5, 6, 7
OPTION
V
CC
INIT
H
L
L
L
L
L
L
H
+5V
X
X
X
X
L
L
L
L
L
L
OE
I10
*
+10V
+10V
X
X
X
X
X
+10V
+10V
X
X
X
X
X
X
X
X
X
I11
*
X
X
+10V
+10V
X
X
X
X
X
+10V
+10V
X
X
X
X
X
X
X
I12
*
X
X
X
X
+10V
X
*
X
X
X
X
+10V
X
X
X
X
X
X
CK
X
J
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
X
K
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
H
X
Q
P
H/L
Q
P
Q
P
L
H
Q
P
Q
P
Q
P
Q
P
Q
P
L
H
Q
P
Q
P
Q
P
L
H
Q
P
H
PLUS405-55
Q
F
H/L
L
H
Q
F
Q
F
Q
F
Q
F
Q
F
L
H
Q
F
Q
F
Q
F
Q
F
Q
F
L
H
Q
F
H
F
Q
F
L
H
L
H
Q
P
Q
F
Hi-Z
L
H
L
H
Q
P
Q
F
Q
F
L
H
Q
F
↑
↑
↑
↑
X
X
X
↑
↑
↑
↑
X
X
↑
↑
↑
↑
X
↑
X
X
NOTES:
1. Positive Logic:
S/R (or J/K) = T
0
+ T
1
+ T
2
+ . . . T
63
T
n
= (C0, C1) (I0, I1, I2, . . .) (P0, P1, . . . P7)
2. Either Initialization (Active-High) or Output Enable (Active-Low) are available, but not both. The desired function is a user-programmable
option.
3.
↑
denotes transition from Low-to-High level.
4. * = H or L or +10V
5. X = Don’t Care (<5.5V)
6. H/L implies that either a High or a Low can occur, depending upon user-programmed selection (each State and Output Register individually
programmable).
7. When using the F
n
pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels
on the output pins are forced by the user.
VIRGIN STATE
A factory-shipped virgin device contains all
fusible links intact, such that:
1. INIT/OE is set to INIT. In order to use the
INIT function, the user must select either
the PRESET or the RESET option for
each flip-flop. Note that regardless of the
user-programmed initialization, or even if
the INIT function is not used, all registers
are preset to “1” by the power-up
procedure.
2. All transition terms are inactive (0).
3. All S/R (or J/K) flip-flop inputs are
disabled (0).
4. The device can be clocked via a Test
Array preprogrammed with a standard
test pattern.
5. Clock 2 is inactive.
LOGIC FUNCTION
Q3
1
Q2
0
Q1
1
Q0
0
S
R
PRESENT STATE
A B C ...
S
n + 1
NEXT STATE
STATE REGISTER
0
0
0
1
⋅ ⋅ ⋅
SET Q
0
: J
0
= (Q
2
Q
1
Q
0
) A B C . . .
K
0
= 0
RESET Q
1
: J
1
= 0
K
1
= (Q
3
Q
2
Q
1
Q
0
) A B C . . .
⋅
⋅
⋅ ⋅ ⋅
⋅
⋅
⋅
⋅ ⋅ ⋅
HOLD Q
2
: J
2
= 0
K
2
= 0
RESET Q
3
: J
3
= (Q
3
Q
2
Q
1
Q
0
) A B C . . .
K
3
= (Q
3
Q
2
Q
1
Q
0
) A B C . . .
⋅
⋅
⋅
⋅
⋅
⋅
⋅ ⋅ ⋅
⋅ ⋅ ⋅
October 22, 1993
182
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer
(16
×
64
×
8)
PLUS405-55
FUNCTIONAL DIAGRAM
P63
I
P0
15
I/CLK
X2
J
(4)
K
P
4
4
Q
R
J
(4)
K
P
4
4
Q
R
J
(4)
Q
4
K
P
4
4
F
R
J
(4)
K
P
4
4
Q
CK
R
4
F
INIT/OE
October 22, 1993
183
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer
(16
×
64
×
8)
PLUS405-55
LOGIC DIAGRAM
DETAIL A
I0 9
I1 8
I2 7
I3 6
I4 5
I5/CLK 4
I6 3
I7 2
I8 27
I9 26
I10 25
I11 24
I12 23
I13 22
I14 21
I15 20
19
INIT/OE
DETAIL B
DETAIL C
18 F0
17 F1
16 F2
15 F3
13 F4
12 F5
11 F6
10 F7
1 CLK
NOTE:
Denotes a programmable fuse location.
DETAIL D
October 22, 1993
184
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