Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
FEATURES
Display
•
50/60 Hz PIP modes possible
•
Twin PIP in interlaced mode at 8-bit resolution
•
Sub-title mode features built in
•
Large display fine positioning area, both channels
independent
•
Only 2 Mbit needed as external VDRAM
(2
×
1 Mbit or 1
×
2 Mbit)
•
Four 8-bit Analog-to-Digital Converters (ADCs; > 7-bit
performance) with clamp circuit
•
Most PIP modes handle interlaced pictures without joint
line error
•
Two PLLs which generate the line-locked clocks for the
acquisition channels
•
Display PLL to generate line-locked clock for the display
•
Three 8-bit Digital-to-Analog Converters (DACs)
•
4 : 1 : 1 data format
•
Data reduction factors 1 to 1, 1 to 2, 1 to 3 and 1 to 4,
horizontal and vertical independent.
I
2
C-bus programmable
•
Single and double PIP modes can be set
•
Full field still mode available
•
Several aspect ratios can be handled
•
Reduction factors can be set freely
•
Selection of vertical filtering type
•
Freeze of live pictures
•
Fine tuned display position, H (8-bit), V (8-bit),
both channels independent
•
Fine tuned acquisition area, H (4-bit), V (8-bit),
both channels independent
•
Eight main borders, sub-borders and background
colours available
•
Border and background brightness adjustable, 30%,
50%, 70% and 100% IRE
•
Several type of decoder input signals can be set.
GENERAL DESCRIPTION
SAB9077H
The SAB9077H is a picture-in-picture controller for
multi-standard TV-sets. The circuit contains ADCs,
reduction circuitry, memory control, display control and
DACs.
It inserts one or two live video signals with original or
reduced sizes into a live video signal. All video signals are
expected to be analog base band signals. The conversion
into the digital environment and back to the analog
environment is done on chip. Internal clocks are generated
by two acquisition PLLs and a display PLL.
The two PIP channels and a large external memory offer a
wide range of PIP modes. The emphasis is put on single
PIP, double PIP, split-screen mode and many multi-PIP
modes.
1996 Aug 07
2
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
PINNING
SYMBOL
MPV
bias
MPH
sync
MAV
SSD
MAV
DDD
MAV
bias
MU
MAV
refT
MV
MAV
refB
MY
MAV
DDA
MAV
SSA
MV
SSD
MV
DDD
MCV
DDD
MCV
SSD
MV
sync
TDCLK
TC
TM0
TM1
TM2
DAI0
DAI7
DAI1
DAI6
DAI2
DAI5
DAI3
DAI4
DT
DAO0
DAO7
DAO1
DAO6
DAO2
DAO5
DAO3
DAO4
SC
1996 Aug 07
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
I/O
I
I/O
I/O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
TYPE
E027
HPP01
E009
E030
E027
E027
E027
E027
E027
E027
E030
E009
E009
E030
E030
E009
HPP01
HPP01
HPP01
HPP01
HPP01
HPP01
HPP04
HPP04
HPP04
HPP04
HPP04
HPP04
HPP04
HPP04
OPF20
OPF20
OPF20
OPF20
OPF20
OPF20
OPF20
OPF20
OPF20
OPF20
DESCRIPTION
analog bias reference for main channel
horizontal synchronization for main channel
SAB9077H
digital ground for main channel ADCs and PLLs
digital positive power supply for main channel ADCs and PLLs
analog bias reference for main channel ADCs
analog U input for main channel
analog top reference voltage for main channel ADCs
analog V input for main channel
analog bottom reference voltage for main channel ADCs
analog Y input for main channel
analog positive power supply for main channel ADCs
analog ground for main channel ADCs
digital ground for main-channel core
digital positive power supply for main-channel core
digital positive power supply for main-clock buffer
digital ground for main-clock buffer
vertical synchronization for main channel
test clock for display
test control
test mode 0
test mode 1
test mode 2
data bus input from memory; bit 0
data bus input from memory; bit 7
data bus input from memory; bit 1
data bus input from memory; bit 6
data bus input from memory; bit 2
data bus input from memory; bit 5
data bus input from memory; bit 3
data bus input from memory; bit 4
memory data transfer output; active LOW
data bus output to memory; bit 0
data bus output to memory; bit 7
data bus output to memory; bit 1
data bus output to memory; bit 6
data bus output to memory; bit 2
data bus output to memory; bit 5
data bus output to memory; bit 3
data bus output to memory; bit 4
memory shift clock output
5
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