INTEGRATED CIRCUITS
DATA SHEET
SAB9082
NTSC Picture-In-Picture (PIP)
controller
Preliminary specification
Supersedes data of 1999 Feb 18
File under Integrated Circuits, IC02
1999 Nov 12
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
FEATURES
•
Double window Picture-in-Picture (PIP) in interlaced or
non-interlaced mode at 8-bit resolution
•
Internal 1-Mbit DRAM
•
Three 8-bit Analog-to-Digital Converters (ADCs) (7-bit
performance) with clamp circuit for each acquisition
channel
•
One PLL which generates the line-locked clocks for the
subchannel
•
One PLL which generates the line-locked clocks for the
main and display channels
•
Three 8-bit Digital-to-Analog Converters (DACs)
•
Linear zoom in both horizontal and vertical directions for
the subchannel
•
Linear zoom in horizontal direction for the main channel
•
Three multistandard PIP modes are available.
GENERAL DESCRIPTION
The SAB9082 is an NTSC PIP controller which can be
used in double window applications. The SAB9082 inserts
one or two live video signals with reduced size into another
live video signal. The incoming video signals are expected
to be analog baseband signals.
SAB9082
The conversion to the digital environment is done on chip
with ADCs. Processing and storage of the video data is
done entirely in the digital domain. The conversion back to
the analog domain is done by means of DACs.
Internal clocks are generated by PLLs which lock on to the
applied horizontal and vertical syncs.
The main input channel is compressed horizontally by a
factor of two and directly fed to the output. After
compression, a horizontal expansion of two is possible for
the main channel.
The subchannel is also compressed horizontally by a
factor of two but stored in memory before it is fed to the
outputs.
The SAB9082 can also create three multistandard PIP
modes, one with three PIPs placed in a column (MP3) and
two with two columns of three PIPs (MP6, MP6S).
The reduction factors of these PIPs are horizontal
1
⁄
4
and
vertical
1
⁄
3
. In the first two modes, the column(s) can be
placed on the left or right side of the screen.
QUICK REFERENCE DATA
SYMBOL
Supply
V
DDD
V
DDA
I
DDD
I
DDA
PLL
f
clk(sys)
B
loop
t
jitter
ζ
system clock frequency
loop bandwidth
short-term stability
damping factor
−
−
peak-to-peak jitter for 64
µs −
−
1792
×
f
HSYNC
28
4
−
0.7
−
−
4
−
MHz
kHz
ns
digital supply voltage
analog supply voltage
digital supply current
analog supply current
3.0
3.0
−
140
3.3
3.3
50
165
3.6
3.6
−
210
V
V
mA
mA
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ORDERING INFORMATION
TYPE
NUMBER
SAB9082H
PACKAGE
NAME
QFP100
DESCRIPTION
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14
×
20
×
2.8 mm
2
VERSION
SOT317-2
1999 Nov 12
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1999 Nov 12
SU
SV
SY
Vbias(SA)
Vref(T)(SA)
Vref(B)(SA)
SHSYNC
SVSYNC
BLOCK DIAGRAM
Philips Semiconductors
VSSA(MA) VDDA(DA) VDDD(DA) VSSD(P1) VDDD(RP) VSSD(RL) VDDD(RM) VDDD(P2)
VDDA(MF) VDDA(MA) VSSA(DA) VSSD(DA) VDDD(P1) VDDD(RL) VSSD(RM) VSSD(RP) VSSD(P2)
3
79
81
83
84
82
80
CLAMP AND ADC
HORIZONTAL
AND
VERTICAL
FILTER
4
5
6
7
14
15
16
17
20
39
40
41
42
61
64
65
handbook, full pagewidth
NTSC Picture-In-Picture (PIP) controller
VSSD(D) VDDA(SA) VDDA(SF) VDDD(SA)
VDDD(D) VSSA(SA) VSSD(SA)
66
67
76
77
78
85
86
8
10
12
DAC AND BUFFER
9
11
13
DY
DV
DU
Vbias(DA)
Vref(T)(DA)
Vref(B)(DA)
87
72
PLL AND CLOCK
GENERATOR
LINE MEMORY
INTERNAL DRAM
DISPLAY
CONTROL
69
68
PKOFF
FBL
VSSD(T1)
and
VSSD(T2)
VSSD(T3)
VSSD(T4)
to
VSSD(T7)
VSSD(T8)
and
VSSD(T9)
DCLK
TC
T5 to T0
18, 19
3
MU
MY
MV
Vbias(MA)
Vref(T)(MA)
Vref(B)(MA)
DHSYNC
DVSYNC
2
98
100
97
99
1
CLAMP AND ADC
HORIZONTAL
FILTER
2
30
SAB9082
4
48 to 51
62, 63
94
70
PLL AND CLOCK
GENERATOR
19
89
VDDA(SP)
90
91
92
95
96
21 to 29, 31,
52 to 60
n.c.
POR
75
74
73
88
T6
SCL
93
T7
44
TM
43
45
46
47
I
2
C-BUS
CONTROL
TEST
CONTROL
71
38
32 to 37
6
Preliminary specification
MGL582
VSSA(DP)
VDDD(MA)
VSSD(MA)
SDA
TCBD
TCLK
TCBR
SAB9082
VSSA(SP)
VDDA(DP)
TCBC
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
PINNING
SYMBOL
V
ref(B)(MA)
MU
V
DDA(MF)
V
SSA(MA)
V
DDA(MA)
V
DDA(DA)
V
SSA(DA)
DY
V
bias(DA)
DV
V
ref(T)(DA)
DU
V
ref(B)(DA)
V
DDD(DA)
V
SSD(DA)
V
SSD(P1)
V
DDD(P1)
V
SSD(T1)
V
SSD(T2)
V
DDD(RP)
n.c.
V
SSD(T3)
n.c.
T5
T4
T3
T2
T1
T0
TC
V
DDD(RL)
V
SSD(RL)
V
SSD(RM)
V
DDD(RM)
TCLK
TM
TCBD
TCBC
TCBR
V
SSD(T4)
to V
SSD(T7)
1999 Nov 12
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 to 29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 to 51
TYPE
I/O
I
S
S
S
S
S
O
I/O
O
I/O
O
I/O
S
S
S
S
S
S
S
−
S
−
I/O
I/O
I/O
I/O
I/O
I/O
I
S
S
S
S
I
I
I
I
I
S
DESCRIPTION
analog bottom reference voltage for main channel ADCs
analog U input for main channel
analog supply voltage for main channel front-end buffers
analog ground for main channel ADCs
analog supply voltage for main channel ADCs
analog supply voltage for DACs
analog ground for DACs
analog Y output of DAC
input/output analog bias reference voltage for DACs
analog V output of DAC
input/output analog top reference voltage for DACs
analog U output of DAC
analog bottom reference voltage for DACs
digital supply voltage for DACs
digital ground for DACs
digital ground for periphery
digital supply voltage for periphery
digital ground for test
digital ground for test
digital supply voltage for memory periphery
not connected
digital ground for test
not connected
test data input/output bit 5 (CMOS levels)
test data input/output bit 4 (CMOS levels)
test data input/output bit 3 (CMOS levels)
test data input/output bit 2 (CMOS levels)
test data input/output bit 1 (CMOS levels)
test data input/output bit 0 (CMOS levels)
test control input (CMOS levels)
digital supply voltage for memory logic
digital ground for memory logic
digital ground for memory core
digital supply voltage for memory core
test clock input (CMOS levels)
test mode input (CMOS levels)
test control block data input (CMOS levels)
test control block clock input (CMOS levels)
test control block reset input (CMOS levels)
digital ground for test
4
SAB9082
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
SAB9082
SYMBOL
n.c.
V
SSD(RP)
V
SSD(T8)
and V
SSD(T9)
V
DDD(P2)
V
SSD(P2)
V
SSD(D)
V
DDD(D)
FBL
PKOFF
DVSYNC
DCLK
SVSYNC
SCL
SDA
POR
V
DDA(SA)
V
SSA(SA)
V
DDA(SF)
SU
V
ref(B)(SA)
SV
V
ref(T)(SA)
SY
V
bias(SA)
V
SSD(SA)
V
DDD(SA)
SHSYNC
T6
V
DDA(SP)
V
SSA(SP)
V
SSA(DP)
V
DDA(DP)
T7
DHSYNC
V
DDD(MA)
V
SSD(MA)
V
bias(MA)
MY
V
ref(T)(MA)
MV
PIN
52 to 60
61
62 and 63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TYPE
−
S
S
S
S
S
S
O
O
I
I
I
I/O
I/O
I
S
S
S
I
I/O
I
I/O
I
I/O
S
S
I
I/O
S
S
S
S
I/O
I
S
S
I/O
I
I/O
I
not connected
DESCRIPTION
digital ground for memory periphery
digital ground for test
digital supply voltage for periphery
digital ground for periphery
digital ground for digital core
digital supply voltage for digital core
fast blanking control signal output (CMOS levels; +5 V tolerant)
peak off control signal output (CMOS levels; +5 V tolerant)
vertical sync display channel input (CMOS levels; +5 V tolerant)
test clock input (28 MHz; CMOS levels)
vertical sync for subchannel input (CMOS levels; +5 V tolerant)
input/output serial clock (I
2
C-bus; CMOS levels; +5 V tolerant)
input/output serial data/acknowledge output (I
2
C-bus; +5 V tolerant)
power-on reset input (CMOS levels; pull-up resistor connected to V
DD
)
analog supply voltage for subchannel ADCs
analog ground for subchannel ADCs
analog supply voltage for subchannel front-end buffers and clamps
analog U input for subchannel
input/output analog bottom reference voltage for subchannel ADCs
analog V input for subchannel
input/output analog top reference voltage for subchannel ADCs
analog Y input for subchannel
analog bias reference voltage for subchannel ADCs
digital ground for subchannel ADCs
digital supply voltage for subchannel ADCs
horizontal sync input for subchannel (V
i
< V
SHSYNC
)
test data input/output bit 7 (CMOS levels)
analog supply voltage for subchannel PLL
analog ground for subchannel PLL
analog ground for display channel PLL
analog supply voltage for display channel PLL
test data input/output bit 6 (CMOS levels)
horizontal sync input for display channel (V
i
< V
DHSYNC
)
digital supply voltage for main channel ADCs
digital ground for main channel ADCs
analog bias reference voltage for main channel ADCs
analog Y input for main channel
analog top reference voltage for main channel ADCs
analog V input for main channel
1999 Nov 12
5
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