L-TTSI001161BL-2-DB,L-TTSI001161BL-2-DB pdf中文资料,L-TTSI001161BL-2-DB引脚图,L-TTSI001161BL-2-DB电路-Datasheet-电子工程世界

Datasheet> 器件分类 > L-TTSI001161BL-2-DB

文档预览

L-TTSI001161BL-2-DB: 产品描述1k x 1k time-slot interchanger; 文件大小623KB，共61页; 制造商Agere System(LSI Logic)

下载文档选型对比全文预览

L-TTSI001161BL-2-DB概述

1k x 1k time-slot interchanger

文档预览

下载PDF文档

全文
预览

Data Sheet, Revision 3

September 21, 2005

TSI-1

1k x 1k Time-Slot Interchanger

1 Introduction

The last issue of this data sheet was August 31, 2005. A change history is included in Section

11 Change History on page

61.

Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text

are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting or

grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically

mentioned.

This document consists of two major sections:

The

TSI-1

device hardware description. This section contains ball information, operating conditions, dc electrical charac-

teristics, timing diagrams, ac characteristics, and packaging information.

The

TSI-1

device register description. This section contains register information.

1.1 Related Documents

The documentation package for this device consists of the following documents:

The TSI-1 1k x 1k Time-Slot Interchanger Product Brief, the TSI Family Selection Guide, the TSI-1 1k x 1k Time-Slot

Interchanger Data Sheet (this document), and the TSI-1 Time-Slot Interchanger System Design Guide.

These documents are available on the public website shown below.

If the reader displays this document using

Acrobat Reader

, clicking on any blue text will bring the reader to that reference

point.

To access related documents, including the documents mentioned above, please go to the following public website, or con-

tact your Agere representative (see the last page of this document).

http://www.agere.com/telecom/time_slot_interchangers.html

1.2 Block Diagram and High-Level Interface Definition

TEST ACCESS

PORT

TEST PATTERN

MONITOR

TEST PATTERN

GENERATOR

1k x 1k Switch Fabric

RECEIVE

CHI

DATA

STORE

TRANSMIT

CHI

WRITE ADDRESS

COUNTER

CLOCK

GENERATOR

CONNECTION

STORE

READ ADDRESS

COUNTER

MICROPROCESSOR

INTERFACE

Figure 1-1. Block Diagram and High-Level Interface Definition

TSI-1

1k x 1k Time-Slot Interchanger

Data Sheet, Revision 3

September 21, 2005

Table of Contents

Contents

Page

1 Introduction .........................................................................................................................................................................1

1.1 Related Documents .....................................................................................................................................................1

1.2 Block Diagram and High-Level Interface Definition .....................................................................................................1

2 Ball Information ...................................................................................................................................................................7

2.1 Top View Ball Diagram ................................................................................................................................................7

2.2 Package Ball Assignments ..........................................................................................................................................8

2.3 Package Ball Matrix ...................................................................................................................................................10

2.3.1 Top View ..........................................................................................................................................................10

2.3.2 Bottom View .....................................................................................................................................................11

2.4 Ball Types ..................................................................................................................................................................12

2.5 Ball Definitions ...........................................................................................................................................................12

3 Operating Conditions and Reliability ................................................................................................................................15

3.1 Absolute Maximum Ratings .......................................................................................................................................15

3.2 Recommended Operating Conditions .......................................................................................................................15

3.3 Handling Precautions ................................................................................................................................................15

3.4 Thermal Parameters (Definitions and Values) ...........................................................................................................16

3.5 Power Consumption ..................................................................................................................................................17

4 dc Electrical Characteristics .............................................................................................................................................18

5 Timing Diagrams and ac Characteristics ..........................................................................................................................19

6 Register Description .........................................................................................................................................................31

6.1 Device Addressing Notes ..........................................................................................................................................31

6.2 Acronyms Used .........................................................................................................................................................31

6.3 Address Map .............................................................................................................................................................31

6.4 Register Summary .....................................................................................................................................................32

6.5 Global Control Registers ...........................................................................................................................................34

6.6 Connection Store Generator Registers .....................................................................................................................39

6.7 Test Pattern Generator and Monitor Registers ..........................................................................................................44

6.8 Concentration Highway Configuration Registers .......................................................................................................48

7 Switch Fabric Control .......................................................................................................................................................54

8 Connection Store ..............................................................................................................................................................58

9 Outline Diagrams ..............................................................................................................................................................60

10 Ordering Information .......................................................................................................................................................61

11 Change History ...............................................................................................................................................................61

11.1 Navigating Through an Adobe Acrobat Document ..................................................................................................61

Agere Systems Inc.

Data Sheet, Revision 3

September 21, 2005

TSI-1

1k x 1k Time-Slot Interchanger

Table of Contents

(continued)

Contents

Page

Table 2-1. Package Ball Assignments in Signal Name Order.................................................................................................8

Table 2-2. Package Ball Assignments (Top View) ................................................................................................................10

Table 2-3. Package Ball Assignments (Bottom View)........................................................................................................... 11

Table 2-4. Ball Types ............................................................................................................................................................12

Table 2-5. Timing Port ..........................................................................................................................................................12

Table 2-6. Transmit and Receive Concentration Highways ..................................................................................................12

Table 2-7. Control Port..........................................................................................................................................................13

Table 2-8. Initialization and Test Access...............................................................................................................................13

Table 2-9. Power Balls..........................................................................................................................................................14

Table 3-1. Absolute Maximum Ratings .................................................................................................................................15

Table 3-2. Operating Conditions ...........................................................................................................................................15

Table 3-3. ESD Tolerance.....................................................................................................................................................15

Table 3-4. Thermal Parameter Values ..................................................................................................................................16

Table 3-5. Power Consumption ............................................................................................................................................17

Table 4-1. CMOS Inputs .......................................................................................................................................................18

Table 4-2. CMOS Outputs ....................................................................................................................................................18

Table 4-3. CMOS Bidirectionals (DATA[15:0]) ......................................................................................................................18

Table 5-1. CHICLK Timing Specifications .............................................................................................................................19

Table 5-2. MPUCLK Timing Specifications ...........................................................................................................................19

Table 5-3. CMOS Output ac Timing Specification * ..............................................................................................................20

Table 5-4. CHI Interface Timing ............................................................................................................................................21

Table 5-5. CHI 3-State Output Control..................................................................................................................................27

Table 5-6. Microprocessor Port Timing—Read Cycle...........................................................................................................28

Table 5-7. Microprocessor Port Timing—Write Cycle ...........................................................................................................29

Table 6-1. Address Map........................................................................................................................................................31

Table 6-2. Global Registers ..................................................................................................................................................32

Table 6-3. Connection Store Generator Registers................................................................................................................32

Table 6-4. Test Pattern Generator and Monitor Registers ....................................................................................................33

Table 6-5. Concentration Highway Configuration Registers .................................................................................................33

Table 6-6. Switch Fabric Control...........................................................................................................................................33

Table 6-7. Connection Store .................................................................................................................................................34

Table 6-8. Reserved Registers .............................................................................................................................................34

Table 6-9. Version_Control (Read Only)...............................................................................................................................34

Table 6-10. Chip_Identity (Read Only) .................................................................................................................................34

Table 6-11. Summary_Interrupt_Status (Read Only) ............................................................................................................35

Table 6-12. Summary_Interrupt_Mask (Read/Write) ............................................................................................................35

Table 6-13. CPU_Access_Error (CORWN) ..........................................................................................................................36

Table 6-14. CPU_Access_Error_Mask (Read/Write)............................................................................................................36

Table 6-15. Global_Control (Read/Write) .............................................................................................................................37

Table 6-16. PLL_Control (Read/Write) .................................................................................................................................38

Table 6-17. Power_Control (Read/Write)..............................................................................................................................38

Table 6-18. Invalid_Address_Trap (Read Only)....................................................................................................................38

Table 6-19. Scratch_Register (Read/Write)..........................................................................................................................38

Table 6-20. Reserved_0 (Read/Write) ..................................................................................................................................39

Table 6-21. CSG_Control (Read/Write) ................................................................................................................................39

Table 6-22. CSG_Status (Read Only)...................................................................................................................................40

Table 6-23. CSG_Starting_Address (Read/Write) ................................................................................................................40

Table 6-24. CSG_Ending_Address (Read/Write) .................................................................................................................40

Table 6-25. CSG_Write_Enable_Low (Read/Write)..............................................................................................................40

Table 6-26. CSG_Write_Enable_High (Read/Write).............................................................................................................40

Table 6-27. CSG_Seed_Low (Read/Write)...........................................................................................................................41

Table 6-28. CSG_Seed_High (Read/Write)..........................................................................................................................41

Agere Systems Inc.

TSI-1

1k x 1k Time-Slot Interchanger

Data Sheet, Revision 3

September 21, 2005

Table of Contents

(continued)

Tables

Page

Table 6-29. CSG_OR_Mask_Low (Read/Write) ...................................................................................................................41

Table 6-30. CSG_OR_Mask_High (Read/Write) ..................................................................................................................41

Table 6-31. CSG_AND_Mask_Low (Read/Write) .................................................................................................................42

Table 6-32. CSG_AND_Mask_High (Read/Write) ................................................................................................................42

Table 6-33. CS_Stream_Control (Read/Write) .....................................................................................................................42

Table 6-34. CSG_Configuration (Read/Write) ......................................................................................................................43

Table 6-35. TPG_Configuration (Read/Write).......................................................................................................................44

Table 6-36. TPG_User_Pattern (Read/Write) .......................................................................................................................44

Table 6-37. TPM_Configuration (Read/Write) ......................................................................................................................45

Table 6-38. TPM_User_Pattern (Read/Write).......................................................................................................................45

Table 6-39. TPM_Error_Count (Sat/Roll*) ............................................................................................................................46

Table 6-40. TPG_Inject_Error_Count (Write Only) ...............................................................................................................46

Table 6-41. TPG_Data_Invert_Mask (Read/Write) ...............................................................................................................46

Table 6-42. TPM_Status (Read Only)...................................................................................................................................47

Table 6-43. TPM_Status_Mask (Read/Write) .......................................................................................................................47

Table 6-44. Receive_CHI_Configuration (Read/Write) .........................................................................................................48

Table 6-45. Receive_CHI_Status (CORWN) Receive_CHI_Status (CORWN).....................................................................48

Table 6-46. Receive_CHI_Status_Mask (Read/Write)..........................................................................................................49

Table 6-47. Receive_CHI_Global_Configuration (Read/Write) ............................................................................................49

Table 6-48. Transmit_CHI_Configuration (Read/Write) ........................................................................................................50

Table 6-49. Transmit_CHI_Status (CORWN) .......................................................................................................................51

Table 6-50. Transmit_CHI_Status_Mask (Read/Write).........................................................................................................51

Table 6-51. Transmit_CHI_Global_Configuration (Read/Write)............................................................................................52

Table 6-52. Receive_CHI_Time_Slot_Offset (Read/Write)...................................................................................................53

Table 6-53. Transmit_CHI_Time_Slot_Offset (Read/Write)..................................................................................................53

Table 7-1. SF_Status (CORWN) ...........................................................................................................................................54

Table 7-2. SF_Status_Mask (Read/Write) ............................................................................................................................54

Table 7-3. Data_Store_Time_Slot_Capture_Select (Read/Write).........................................................................................55

Table 7-4. Data_Store_Captured_Data (Read Only) ............................................................................................................55

Table 7-5. Connection_Store_Parity_Error_Address_Trap (CORWN) .................................................................................56

Table 7-6. Receive_Link_Offset (Read Only) .......................................................................................................................56

Table 7-7. Transmit_Link_Offset (Read/Write) .....................................................................................................................56

Table 7-8. Wide_Mode_Control (Read/Write).......................................................................................................................57

Table 8-1. Low_Control_Word (Read/Write).........................................................................................................................58

Table 8-2. High_Control_Word (Read/Write) ........................................................................................................................59

Table 10-1. Ordering Information..........................................................................................................................................61

Agere Systems Inc.

Data Sheet, Revision 3

September 21, 2005

TSI-1

1k x 1k Time-Slot Interchanger

Table of Contents

(continued)

Figures

Page

Figure 1-1. Block Diagram and High-Level Interface Definition..............................................................................................1

Figure 2-1. Package Diagram (Top View) ..............................................................................................................................7

Figure 5-1. CHICLK Timing Specifications ...........................................................................................................................19

Figure 5-2. MPUCLK Timing Specifications .........................................................................................................................19

Figure 5-3. ac Timing Specification ......................................................................................................................................20

Figure 5-4. CHI Interface Timing ..........................................................................................................................................21

Figure 5-5. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK.............................................22

Figure 5-6. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK ........................................................22

Figure 5-7. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK...............................................23

Figure 5-8. Transmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK ..........................................................23

Figure 5-9. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK...............................................24

Figure 5-10. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK ........................................................24

Figure 5-11. Typical Receive CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK.............................................25

Figure 5-12. Transmit CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK ........................................................25

Figure 5-13. Typical Receive CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK...............................................26

Figure 5-14. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK ..........................................................26

Figure 5-15. CHI 3-State Output Control ..............................................................................................................................27

Figure 5-16. Microprocessor Port Timing—Read Cycle .......................................................................................................28

Figure 5-17. Microprocessor Port Timing—Write Cycle .......................................................................................................29

Figure 6-1. Transmit CHI Configuration (R/W) .....................................................................................................................50

Agere Systems Inc.

L-TTSI001161BL-2-DB相似产品对比

	L-TTSI001161BL-2-DB	TTSI001161BL-2-DB
描述	1k x 1k time-slot interchanger	1k x 1k time-slot interchanger

推荐资源

#闲置市集#开集了，你出闲置我送礼!: 437936 在这些年的工作和学习中，大家一定积累了不少开发板和有意思的“小玩具”吧！有没有已经闲置许久计划“断、舍、离”的？也许在你那里的闲置 ......; eric_wang 淘e淘

大家好，本人要参加9月份的全国大学生电子设计竞赛，最近论坛来的少，请见谅。。。: 本帖最后由 paulhyde 于 2014-9-15 09:20 编辑大家好，本人要参加9月份的全国大学生电子设计竞赛，最近论坛来的少，请见谅。。。给您带来的不便，还望海涵。如有急切的问题要解决，可以呼我 ......; 破茧佼龙电子竞赛

基于CAN总线的多功能汽车行驶记录仪设计: 1. 概述汽车行驶记录仪，又称“汽车黑匣子”，是对车辆行驶速度、时间、里程以及有关车辆行驶的其他状态信息进行记录、存储并可通过接口实现数据输出的数字式电子记录装置。多功能汽车行驶记录 ......; frozenviolet 汽车电子

HardFaultException: 请教斑竹：我有一块ST32103ZE的评估板,通过realview可以下载,也可以跑起来,但就是不能调试,具体现象是:按下ctrl+F5健,直接跳到HardFaultException,没有跳到我设的断点处,请教斑竹是哪里有 ......; zsmbj stm32/stm8

如何將應用程序源碼放入PB中，作為PB的組件一起編譯: 如何將應用程序源碼放入PB中，作為PB的組件一起編譯。就好像加入自己開發的組件一樣。然后，讓應用程序能夠正常在編譯後運行......; alongzy 嵌入式系统

四轴飞行器跟踪用什么传感器？: 我想实现第一架飞行器用遥控器，第二架飞机自动跟随第一架飞行器飞行，不知道用什么传感器？我想用摄像头，但是图像处理太复杂，还有其他传感器可以用吗？...; dhx518 传感器

基于FPGA的核物理实验定标器的设计实现

　　定标器在大学实验中有很广泛的应用，其中近代物理实验中的核物理实验里就有2个实验（G-M计数管和β吸收）要用到高压电源和定标器，而目前现有的设备一般使用的是分立元器件，已严重老化，高压极不稳定，维护也较为困难；另一方面在许多常用功能上明显欠缺，使得学生的实验课难以维持。为此我们提出了一种新的设计方案：采用EDA进行结构设计，充分发挥FPGA（Field Programmable Gate Ar...[详细]
医疗器械产品的人机界面设计与控制

　　虽然不当的医械产品设计并不总是和医械产品相关失误联系在一起的。对用户的研究表明，缺乏足够的培训占此类失误原因的70％到90％。但是即便这些责任人可能已经被“责罚”了，还是存在其它对病人造成危害的因素，其中之一就是不当的人机界面设计很多失曝都是隐藏在常规的医疗工作和医械产品使用之中，给不知情的医生和病人带来灾难。医疗器械与用户有直接关系的就是医疗器械的人机界面。人机界面设汁的优劣关系到医...[详细]
手机无线芯片出货量放缓但前景可期

　　市场研究集团Forward Concepts通过对WSTS的最新半导体出货量统计数据进行分析，认为尽管出现了手机芯片的出货量放缓现象，但对统计的数据表示质疑。　　手机专用DSP和RISC芯片的五月份出货量比四月份增加了8%，从去年五月份累计增长率为47%。　　Forward Concepts的总裁Will Strauss同时也指出，WSTS的报告称用于无线设备的DSP五月份出货量比四...[详细]
DSP与模拟技术加速医疗电子发展

　　TI认为医疗器械在未来几年内的最大变化就是无线连接技术。它包括含远程病人监控在内的不同应用，其中远程病人监控功能将帮助医务人员无需让病人走进医院即可搜集监测其相关信息。无线连接技术与可植入设备的结合将使功能正常的大脑绕过脊椎断开部位直接连接并支配功能正常的四肢。　　应用无线连接技术可对药物释放系统进行监测、控制和优化。总之，无线连接技术将使医疗器械与决策者之间做到信息共享。可植入设备是另...[详细]
医疗影像存储与传输左右信息化进程

　　医疗信息化需要对数据资产的管理有一个通盘的考虑。　　在在去年本刊举办的“富营”活动中，曾有多数医疗行业CIO表示，目前国内80%的医院已经实施管理信息系统（MIS），系统建设状况相对成熟；而HCIS（临床管理信息化系统）则相对不足。人们普遍关注的电子病历系统、医疗影像存储与传输系统（PACS）系统以及临床决策支持系统，其中绝大部分尚处于部分应用或试用探索阶段，近半数医院仍是空白。　　...[详细]
最新技术为ADC器件发展注入强劲动力

　　10多年来，模数转换器(ADC)作为产业发展助力剂已在工业过程控制、医疗仪器、通信系统和雷达等产品中得到广泛应用。其参数性能的不断提高使得这些‘蓝领’器件能紧跟上最新技术要求。　　2007年2月份在旧金山举办的国际固态电路会议(ISSCC)展示了ADC的丰收成果。有关Nyquist Track的大量论文重新定义了这方面的技术发展水平，其中有两个已进入新的领域。另外也不要忘记来自一般怀疑者...[详细]
PSoC电容式触摸感应技术

　　PSoC是由Cypress半导体公司推出的具有数字和模拟混合处理能力的可编程片上系统芯片，某些系列的PSoC（如CY8C21X34系列），由于其内部配备的特殊资源，使得它可以很容易地实现电容式触摸感应功能，仅需少量的几个外置分立元件，可以将每一个通用的I/O都配置为电容感应输入。　　电容式触摸感应原理如图1所示，电路板上两块相邻的覆铜之间存在一个固有的寄生电容Cp，当手指（或其他导体）靠近时...[详细]
面向21世纪的医疗卫生革新

　　全球医疗行业的三大威胁　　从全球范围来看，医疗行业面临着三大威胁。首先看安全问题。在美国每年因为医疗事故死亡的数字相当惊人，由于不完善的医疗服务所造成的死亡数字也是触目惊心。因医疗事故引起的病人死亡人数达到15万到20万，因不能得到足够好和足够多的医疗服务而导致死亡的人数达6万。其次，医疗成本问题。近几年世界范围内的医疗成本在急剧上升，无论是从美国，还是从美国以外的其他国家来看，医疗成本...[详细]
正电子发射计算机断层成像(PE)

　　医疗成像正在取得显著进步。正电子发射计算机断层成像有助于检查患者体内的组织活动。ST提供从分立器件到32位数字处理器和存储器的广泛产品组合，帮助进一步加强磁共振成像应用。以下结构方块图可帮助您在众多推荐的适用产品中进行选择。 ...[详细]
基于RF收发器的植入式医疗设备通信

　　Zarlink Semiconductor公司针对起搏器、神经刺激器、药泵以及其他此类植入式应用医疗设备的一款超低功率RF收发器芯片，其数据传输率高、功耗低，具有独特的唤醒电路。本文讨论了如何采用这款RF收发器实现体内通信系统的设计。　　集成电路(IC)和医疗设备的开发在过去30年同时得到了发展。电路技术的发展促使了日益复杂、高度集成和小型化医疗器械的发展。同时，保健成本的不断...[详细]
飞兆的电平转换器简化SD卡应用设计

飞兆半导体公司 (Fairchild Semiconductor) 推出专为安全数字 (SD) 应用的设计人员而设能够简化其设计的低电压、双电源 SD 接口电平转换 FXL2SD106 ，具备内置的自动方向控制功能，可让器件感测和控制数据流动的方向，而无需方向控制接脚。这种自动方向控制功能降低了设计的复杂性，无需对控制方向的通用 I/O 接口 (GPIO) 进行编程...[详细]
美国国家半导体公司的SolarMagic技术

SolarMagic Raceway 　　画面是我们在"31号停车场"上铺设的SolarMagic赛车道。车道上停放的两辆高尔夫球车都在车顶安装设了先进的光伏太阳能电池板。停在左方的黄色赛车采用传统的太阳能技术，而停在右方的蓝色赛车采用美国国家半导体公司的SolarMagic技术。车道上搭建了几个拱门架，在架下有太阳投射的阴影。两条车道完全相同，拱门架下格子图案的阴影也相同。　　当高尔...[详细]
数字信号处理（DSP ）系统测试和调试2

　　JTAG 技术简介　　收缩技术(shrinking technology)的一个劣势在于，测试小型器件的复杂程度急剧升高。当电路板面积较大时，板的测试是通过采用钉床等技术来进行的。这种技术采用小型弹簧式测试探针来和板底部的焊盘进行连接。这种测试方案是定制的，不仅成本太高，而且效率低下，而且在设计完成之前很多测试都无法进行。　　随着电路板面积的缩小，以及表面贴装技术的改进，钉床测试的问题不...[详细]
台湾松绑半导体面板赴大陆投资延后至9月

　　据我国台湾媒体报道，原定于8月松绑的台湾半导体及面板前端行业赴大陆投资政策将延后，“应该在9月可以松绑”。　　中国台湾“经济部”原定于8月松绑包括半导体晶圆厂、面板前端、石化等几个重要产业的赴大陆投资政策的限制，目前这一计划面临暂缓。“经济部长”尹启铭近日表示，经过评估与考虑，台湾当局决定暂缓这项计划，至于延后时间，“应该在9月可以松绑”。　　马英九近日表示，台湾开放12寸晶圆厂制造...[详细]
泰克公司数字视频仪器成网通奥运会首选

中国领先的宽带通信运营商将使用获奖的泰克公司视频测试设备，以传送完美的视频信号。俄勒冈州比佛顿，2008年6月24日，全球领先的测试测量和监测仪器供应商泰克公司今天宣布，中国网通（China Netcom, CNC）决定采用泰克公司的视频测试和测量设备，以确保北京2008奥运会视频信号的高质量传送。中国网通选购的泰克公司视频测试设备有新型的PQA500图像质量分析仪、WFM7...[详细]

器件捷径: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多