OX16PCI958
DATA SHEET
Octal UART
with PCI Interface
F
EATURES
•
Efficient 32-bit, 33
1
/
3
MHz multi-function, target-only
PCI controller, compliant to PCI Local Bus
Specification 3.0 & PCI Power Management
Specification 1.1
Eight UARTs fully software compatible with 16C550-
type devices
Compatible with existing 16C550/450 device drivers
PCI 2.1, 2.2, 2.3 & 3.0 compliant
Supports both 5.0-V & 3.3-V PCI signalling
32-byte deep FIFO per transmitter & receiver
Baud rates up to 4.125 Mega-baud (using a
16.5 MHz input clock).
Clock can be provided from crystal oscillator or
external clock source
Automated out-of-band flow control using
CTS#/RTS#
Configuration data is held in a small, low-cost serial
Microwire
TM
compatible EEPROM
•
•
•
•
Driver-facilitated DSR/DTR & Xon/Xoff handshaking
5-,6-,7- & 8-bit data framing
1, 1.5 or 2 stop bits
UART enhancements:
•
Clock prescaler allows more baud rate options
•
Readable FIFO levels & tuneable trigger levels
improve device driver performance
•
Programmable “synchronization factor” allows
baud rates up to fclock/4
•
Extensions to standard register set are
implemented in a safe, easy-to-use way
Low-power design with separate power management
control
Operating temp. range : 0
o
C—70
o
C
160-pin QFP package
Operation via IO or memory mapping
Support for multiple wake-up events
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D
ESCRIPTION
The OX16PCI958 contains eight UARTs (Universal
Asynchronous Receiver-Transmitters) and a host
interface suitable for direct connection to a PCI bus.
Once installed and configured by the host OS, it provides
an eight-byte programming interface to each UART. The
UARTs are fully software-compatible with 16C550
devices. The device can be configured to fit the
requirements of RS232 or RS422 applications.
The UARTs convert between RS232-format serial data
on separate transmit and receive lines, and byte-wide I/O
writes and reads on the host interface. Malformed
incoming serial data is flagged along with the data in the
receive FIFO. The state of the UART can be found at
any time by reading status registers, and modem control
(handshaking output) lines can be individually controlled.
Although polled-mode operation is possible, the UART
will usually be operated on a host-interrupt basis. The
interrupt system is designed to allow efficient handling of
interrupt service requests from the UART, for example by
using the prioritised interrupt identification register,
readable FIFO levels, and tuneable FIFO trigger levels.
The internal transmitter and receiver logic runs at a
programmable synchronisation factor of 4x, 8x, or 16x
the serial baud rate. This internal clock is generated by
dividing a reference clock by an integer divisor from 1 to
(2
16
–1). In this way the UART can accommodate a serial
rate of up to 4 125 000 baud (using a 16.5 MHz input
clock).
The OX16PCI958 provides a host interface that can be
directly connected to a PCI bus. It responds to
configuration accesses, and once configured it also
responds to I/O and memory accesses for control of the
UART. The data for configuration space is read from a
small external serial EEPROM at start-up, together with
information on how the OX16PCI958 should be set up.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900
External—Free Release
Oxford Semiconductor 2005
OX16PCI958 DS-0022—Nov 2005
Part No. OX16PCI958—PQAG
OXFORD SEMICONDUCTOR LTD.
OX16PCI958 DATA SHEET
C
ONTENTS
Features
Description
Contents
1.
Block Diagram
2.
Pin Information—160-pin QFP
2.1. Pinout
2.2. Pin Descriptions
3.
PCI interface
3.1. Internal Address Map
3.2. Configuration & Control Registers
3.3. PCI Configuration Space Registers
3.4. PCI Set-up Registers
4.
UART function
4.1. Programming
4.2. Accessible Registers
4.3. Serial Data Format
4.4. Transmitter/Receiver Section
4.5. FIFO Interrupt Mode Operation
4.6. FIFO Polled Mode Operation
4.7. Loopback Mode
4.8. Auto Flow Control
4.8.1. Auto-RTS
4.8.2. Auto-CTS
4.8.3. Enabling Auto-RTS & Auto-CTS
4.9. Chip Type Identification
4.10.
SISR Function
5.
EEPROM
5.1. The EEPROM Reader
5.2. EEPROM Data Format
5.3. Example EEPROM Data
6.
Clock/Oscillator Pins
7.
Operating conditions
7.1. Recommended Operating Conditions
7.2. DC Characteristics
8.
I/O electrical & timing specifications
9.
Package information
10.
Glossary
11.
Ordering information
12.
Contact Details
1
1
2
3
4
4
5
7
7
9
11
15
16
16
16
21
21
24
25
26
27
28
28
28
29
30
31
31
32
33
35
36
36
36
37
43
44
45
46
DS-0022 Nov 05
External—Free Release
Page 2
OXFORD SEMICONDUCTOR LTD.
OX16PCI958 DATA SHEET
2.2.
Pin Descriptions
Table 1 lists the pin allocations, names and describes them.
Table 1 Pin Descriptions
Name
PAR
CLK
RST#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
INTA#
PME#
IDSEL
AD[31:0]
C/BE#3
C/BE#2
C/BE#1
C/BE#0
EECS
EECK
EEDIO
XTALI
XTALO
LD_EN
VSS (GND)
VDD (5V)
VDDP
22
145
144
13
14
16
17
18
19
21
143
146
160
Pin
IO
I
I
I
I
OT
OT
OT
OT
OT
OT
OT
I
Dir
Description
PCI bus signals
148, 149,150, 152, 153, 154, 155, 157, 1, 3, 4, 5, 7, 8, 9, 10,
25, 26, 27, 28, 30, 31, 32, 34, 36, 37, 39, 40, 41, 43, 44, 45 IO
159
12
23
35
53
52
50
78
79
140
I
I
I
I
Chip configuration
O
O
IO
Local clock
I
O
Local side
O
Power and ground
6, 15, 24, 33, 42, 49, 51, 60, 69, 77, 88, 97, 106, 115, 124, 134, 142, 151, 158
56, 65, 74, 84, 93, 102, 111, 120, 129, 138
2, 11, 20, 29, 38, 46, 47, 141, 147, 156
The VDDP pins provide power to the PCI I/O buffers, and must be connected to the +V
I/O
pins
on the PCI connector.
Table 2 &
DS-0022 Nov 05
External—Free Release
Page 5
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