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Description
The MK2042-01 is designed to switch between
two clock sources. The switching can be externally
controlled by an input pin or configured to switch
automatically if the primary input clock stops.
The part also provides clock detection by reporting
when the primary input clock has stopped.
The MK2042-01 is optimized for use with our
MK2049 family of Communication Clock
Synthesizers. When used together, the
MK2042-01 and MK2049 provide a complete
system for switching to an alternate source when
the primary clock is lost, or for maintaining a
stable frequency on the MK2049 output.
For switching between clock sources with no
output glitches or short pulses, use the ICS580 or
ICS581 multiplexers.
MK2042-01
Communications Clock Monitor
Features
• Packaged in 16 pin SOIC
• User controlled or automatic switching
• Clock detect feature
• Does not add jitter or phase noise to the clock
• Ideal for systems with backup or redundant clocks
• Selectable timeouts for clock loss detection
• Accepts input frequencies from 0 Hz to 160 MHz
• Works with all MK2049-xx to provide enhanced
operation
• 3.3 V or 5 V operation
Block Diagram
VDD
GND
SELB
OE
INB
INA
Clock Loss
Detector
CLKOUT
NO_INA
REFIN
S2:S0
CENTER
3
VDD
HIGH
LOW
GND
1
Revision 102600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2042-01
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Pin Assignment
S0
S1
S2
INB
INA
GND
SELB
REFIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OE
VDD
CLKOUT
NO_INA
HIGH
LOW
GND
CENTER
MK2042-01
Communications Clock Monitor
Clock Loss Detector Settings
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Nominal Count
34
18
130
66
10
6
2
2
16 pin (150 mil) SOIC
Due to the possible phase differences between
the REFIN clock and the INA clock, the
Nominal Count has a tolerance of -0/+1
REFIN clock edges.
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
S0
S1
S2
INB
INA
GND
SELB
REFIN
CENTER
GND
LOW
HIGH
NO_INA
CLKOUT
VDD
OE
Type
I
I
I
I
I
P
I
I
I
P
O
O
O
O
P
I
Description
Clock Count Select 0. Determines allowed number of missing clock edges per table above.
Clock Count Select 1. Determines allowed number of missing clock edges per table above.
Clock Count Select 2. Determines allowed number of missing clock edges per table above.
Input Clock B.
Input Clock A.
Connect to ground.
Mux select. Selects INB when high.
Reference Clock Input.
Enables HIGH and LOW pins when high.
Connect to ground.
Sets low end of centering range.
Sets high end of centering range.
Goes high when clock on INA stops.
Clock output.
Connect to +3.3 V or +5 V.
Output Enable. Tri-states CLKOUT when low.
Type: I = Input, O = output, P = power supply connection
All inputs have an internal pull-up.
2
Revision 102600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2042-01
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Electrical Specifications
Parameter
Supply Voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage Temperature
Operating Voltage, VDD
Input High Voltage, VIH (Note 2)
Input Low Voltage, VIL (Note 2)
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH, CMOS level
Output High Voltage, VOH
Output Low Voltage
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance
Input Frequency, External Mode
Input Clock Pulse Width
CLKOUT Settling Time
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, High Time
Conditions
MK2042-01
Communications Clock Monitor
Minimum
Typical
Maximum
7
VDD+0.5
85
250
150
5.25
(VDD/2)-1
Units
V
V
°C
°C
°C
V
V
V
V
V
V
V
V
mA
mA
pF
MHz
ns
ms
ns
ns
%
ABSOLUTE MAXIMUM RATINGS (Note 1)
Referenced to GND
-0.5
-40
Max of 10 seconds
-65
3.14
(VDD/2)+1
2
0.8
IOH=-4 mA
IOH=-8 mA
IOL=8 mA
No Load, VDD=3.3 V
Each output
VDD-0.4
2.4
0.4
5
±50
7
0
4
100
1
1.5
1.5
60
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
INA, INB
INA, INB
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
INA, INB, REFIN
After SELB change
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
40
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Switching occurs nominally at VDD/2.
3: The phase relationship between input and output clocks can change at power up or when switching between INA and INB.
EXTERNAL COMPONENT SELECTION
The MK2042-01 requires a minimum number of external components for proper operation. A decoupling
capacitor of 0.01µF must be connected between VDD and GND, pins 15 and 10. This capacitor should be
as close to the chip as possible. A series termination resistor of 33
Ω
may be used on CLKOUT with traces
longer than 1 inch (assuming 50
Ω
traces). In applications where the HIGH and LOW outputs are
connected to the MK2049-xx, 10 kΩ resistors should be used on each of those outputs.
3
Revision 102600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2042-01
ADVANCE INFORMATION
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LOC K
DETECTING CLOCK LOSS
MK2042-01
Communications Clock Monitor
The MK2042-01 internal Clock Loss Detector compares the REFIN clock to the INA clock to determine
when the INA clock is no longer present. During normal operation, the Detector is reset with each rising
edge of the INA clock, and the NO_INA output will remain low. In a fault condition where the INA
clock is removed, the Detector will use the REFIN clock to wait the pre-determined number of REFIN
clock pulses (set by S2:S0 per the table on page 2), and will then force the NO_INA output to a high level.
The NO_INA signal can be used to notify the system that the input clock has been lost, or it can provide
automatic switchover to INB. Automatic switchover to INB is achieved by connecting NO_INA to the
SELB input, as illustrated in Figure 1. In this case the MK2042-01 will automatically switch CLKOUT to
the INB input when the loss of INA is detected. With this configuration, when INA becomes active again,
NO_INA will go low and the MK2042-01 will switch CLKOUT to INA. Since the Clock Loss Detector
will set NO_INA low as soon as an INA clock edge occurs, sporadic edges on INA could cause CLKOUT
to switch unpredictably between INA and INB. Because of this, external system control of SELB is best in
cases where the INA clock is sporadic.
Note that proper operation of the Clock Loss Detector requires that there always be a clock on REFIN.
The REFIN clock does not need to be the same frequency as the INA clock. Because the REFIN clock and
the INA clock are asynchronous, the Clock Loss Detector Count shown in the table on page 2 has a
tolerance of -0/+1 REFIN clock edges.
4
Revision 102600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2042-01
ADVANCE INFORMATION
I C R O
C
LOC K
MK2042-01
Communications Clock Monitor
VDD
S0
S1
S2
INB
INA
GND
SELB
REFIN
OE
VDD
0.01µF
CLKOUT
NO_INA
10 kΩ
HIGH
LOW
10 kΩ
GND
CENTER
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8K
8 kHz clock
from network
FS0
RES
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
FS2
In this configuration, the output
frequency of the MK2049-34
will be held at the nominal
value after missing 2 cycles of
the 8 kHz network clock.
(Not all connections for
MK2049-34 are shown.)
Figure 1.
MDS 2042-01
Typical Application of MK2042-01 With MK2049-34
5
Revision 102600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
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