笙泉科技股½有限公司
Megawin Technology Co., Ltd.
MG87FE/L2051/4051/6051
Data Sheet
Ver 1.03
This document information is the intellectual property of Megawin Technology.
©
Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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MEGAWIN
MAKE YOU WIN
MG87FE/L2051/4051/6051
Preliminary, v 1.03
Content
1.
2.
3.
4.
5.
General Description ..................................................................................... 4
Features ....................................................................................................... 5
Block Diagram.............................................................................................. 6
Pin Configurations........................................................................................ 7
4.1. Package Instruction .............................................................................................................. 7
4.2. Pin Description (PDIP-20 & SOP-20).................................................................................... 8
8051 CPU Function Description................................................................... 9
5.1. CPU Register ........................................................................................................................ 9
5.2. CPU Timing......................................................................................................................... 10
5.3. CPU Addressing Mode ....................................................................................................... 10
6.
7.
8.
Memory Organization................................................................................. 11
6.1. On-Chip Program Flash ...................................................................................................... 11
6.2. On-Chip Data RAM ............................................................................................................. 12
Special Function Register .......................................................................... 13
7.1. SFR Map............................................................................................................................. 13
7.2. SFR Bit Assignment............................................................................................................ 14
Configurable I/O Ports................................................................................ 16
8.1. IO Structure......................................................................................................................... 16
8.1.1. Port1/3/4 GPIO Structure ............................................................................................. 16
8.2. Port1 Register ..................................................................................................................... 16
8.3. Port3 Register ..................................................................................................................... 16
8.4. Port4 Register ..................................................................................................................... 17
9.
Interrupt...................................................................................................... 18
9.1. Interrupt Structure ............................................................................................................... 18
9.2. Interrupt Register ................................................................................................................ 19
10. Timers/Counters......................................................................................... 23
10.1. Timer0 and Timer1.............................................................................................................. 23
10.1.1. Mode 0 Structure.......................................................................................................... 23
10.1.2. Mode 1 Structure.......................................................................................................... 23
10.1.3. Mode 2 Structure.......................................................................................................... 24
10.1.4. Mode 3 Structure.......................................................................................................... 24
10.1.5. Timer0/1 Register......................................................................................................... 25
10.2. PWM-Timer......................................................................................................................... 27
10.2.1. PWM-Timer Structure................................................................................................... 27
10.2.2. PWM-Timer Register .................................................................................................... 28
11. UART ......................................................................................................... 30
11.1. UART Structure................................................................................................................... 30
11.2. UART Register.................................................................................................................... 31
12. Analog Comparator .................................................................................... 33
12.1. Analog Comparator Structure ............................................................................................. 33
12.2. Analog Comparator Register .............................................................................................. 34
13. Watch Dog Timer (WDT)............................................................................ 35
13.1. WDT Structure .................................................................................................................... 35
13.2. WDT Register ..................................................................................................................... 35
This document information is the intellectual property of Megawin Technology.
©
Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
2/56
MEGAWIN
MAKE YOU WIN
MG87FE/L2051/4051/6051
Preliminary Ver 1.00
14. Reset.......................................................................................................... 37
14.1. Reset Source ...................................................................................................................... 37
15. Power Management ................................................................................... 38
15.1. Power Saving Mode............................................................................................................ 38
15.1.1. Idle Mode...................................................................................................................... 38
15.1.2. Power-down Mode ....................................................................................................... 38
15.1.3. Interrupt Recovery from Power-down........................................................................... 38
15.1.4. Reset Recovery from Power-down............................................................................... 39
15.1.5. GPIO wake-up Recovery from Power-down................................................................. 39
15.2. Power Control Register....................................................................................................... 39
16. System Clock ............................................................................................. 41
16.1. Clock Structure ................................................................................................................... 41
16.2. Clock Register..................................................................................................................... 41
17.
18.
19.
20.
21.
22.
In System Programming (ISP) ................................................................... 43
In Application Programming (IAP).............................................................. 45
Auxiliary SFRs............................................................................................ 46
Option Setting ............................................................................................ 48
Absolute Maximum Rating ......................................................................... 49
Electrical Characteristics............................................................................ 50
22.1. DC Characteristics .............................................................................................................. 50
23. Package Dimension ................................................................................... 51
24. Instruction Set ............................................................................................ 53
25. Revision History ......................................................................................... 56
This document information is the intellectual property of Megawin Technology.
©
Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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MEGAWIN
MAKE YOU WIN
MG87FE/L2051/4051/6051
Preliminary, v 1.03
1. General Description
MG87FE/L2051/4051/6051
is single-chip 8-bits microcontroller with the instruction sets fully compatible with
industrial-standard 80C51 series microcontroller.
2K/4K/6K
bytes flash memory and 256 bytes RAM has been
embedded to provide widely field application. In-System-Programming and In-Application-Programming allows
the users to download new code or data while the microcontroller sits in the
application. This device executes
one machine cycle in 6 clock cycles or 12 clock cycles. MG87FE/L2051/4051/6051 has one 8-bit I/O ports (P1),
one 7-bit I/O port (P30~P35,P37), two 16-bit timer/counters, one PWM-timer
for 8-channel PWM output, a seven
-source, four-priority-level interrupt structure, an enhanced UART, a precision analog comparator, on-chip crystal
oscillator(combined P42,P43) and a high-precision internal oscillator.
This document information is the intellectual property of Megawin Technology.
©
Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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MEGAWIN
MAKE YOU WIN
MG87FE/L2051/4051/6051
Preliminary Ver 1.00
2. Features
80C51 Central Processing Unit
MG87FE/L2051 with 2KB flash ROM, 4051/4KB flash ROM; 6051/6KB flash ROM
Operating voltage: E type: 4.5V~5.5V and L type: 2.4V~3.6V
Operation frequency :
48MHz(max)@12T
and 24MHz@6T mode
-
-
External crystal mode
Internal RC-oscillator with +/- 4% frequency drift @ -40 ~ 85℃, there are 6 kinds of frequencies
selectable:
Internal oscillator frequency
1
2
3
4
5
6
6MHz
11.059MHz
12MHz
22.118MHz
24MHz
24.576MHz
ISP memory zone could be optioned as 0.5K/1KB/1.5KB~3.5KB
IAP capability; 1KB IAP memory size
On-chip 256 bytes data RAM for MG87FE/L2051/4051/6051
Code protection for flash memory access
Two 16-bit timer/counter
PWM-Timer for PWM generator or normal 8-bit timer, selectable interrupt on INT3
Seven sources, four-level-priority interrupt capability.
Enhanced UART, provides frame-error detection and hardware address-recognition
15 bits Watch-Dog-Timer with 8-bit pre-scalar, one-time enabled by CPU or power-on
Power control: idle mode and power-down mode, Power-down can be woken-up by INT0(P3.2), INT1(P3.3),
INT2(P4.3), INT3(P4.2) and other I/O.
I/O port list, P1[7:0], P3[7,5:0], P4.2/INT3 on XTAL2, P4.3/INT2 on XTAL1
Built-in analog comparator with selectable interrupt on INT2. AIN0(V+) on P1.0 and AIN1(V-) on P1.1,
output on P3.6
Package type: PDIP-20, SOP-20
Items
MG87Fxy051AE20
MG87Fxy051AS20
Package Type
PDIP-20
SOP-20
Description
x = E:5.0V , L:3.3V
y = 2, 4, 6 . 2051/4051/6051
This document information is the intellectual property of Megawin Technology.
©
Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
5/56