U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
©1999-2003
H
OST
I
NTERFACE
As summarized in the table below, UC1606
supports two 8-bit parallel bus protocols and two
serial bus protocols. Designers can choose either
Bus Type
PS[1:0]
CS[1:0]
CD
WR0
WR1
Access
D[7:0]
8080
10b
6800
11b
the 8-bit parallel bus to achieve high data transfer
rate, or use serial bus to create compact LCD
modules and minimize connector pins.
SPI(S9)
01b
–
0
0
Control & Data Pins
SPI (S8)
00b
Chip Select
Control/Data
_ _
___
__
WR
___
__
R/W
EN
0
0
RD
Read/Write
Write Only
8-bit bus (Tri-state)
D0=SCK, D2=SDA
* Connect unused control pins to V
DD
or V
SS.
Table 4:
Host interfaces Choices
P
ARALLEL
I
NTERFACE
The timing relationship between UC1606 internal
control signal RD, WR and their associated bus
actions are shown in the figure below.
The Display RAM read interface is implemented as
a two-stage pipeline. This architecture requires that,
every time memory address is modified, either in
External
CD
___
WR
parallel mode or serial mode, by either
Set CA
or
Set PA
command, a dummy read cycle need to be
performed before the actual data can propagate
through the pipeline and be read from data port
D[7:0].
There is no pipeline in write interface of Display
RAM. Data is transferred directly from bus buffer to
internal RAM on the rising edges of write pulses.
__
RD
D[7:0]
L
LSB
D
L
D
L+K
C
MSB
C
LSB
Dummy
D
C
D
C+1
M
MSB
M
LSB
Internal
Write
Read
Data
Latch
Column
Address
L
D
L
L+K
D
L+K
L+K+1
Dummy
C
D
C
C+1
D
C+1
C+2
D
C+2
C+3
M
Figure 4:
Parallel Interface & Related Internal Signals
20
Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
S
ERIAL
I
NTERFACE
UC1606 supports two serial modes, 4-wire mode
(PS=”LL”), and 3-wire mode (PS=”LH”). The mode
of interface is determined during power-up process
by the value of PS[1:0].
4-
WIRE
S
ERIAL
I
NTERFACE
(S8)
Only write operations are supported in 4-wire serial
mode. Pin CS[1:0] are used for chip select and bus
cycle reset. Pin CD is used to determine the
content of the data been transferred. During each
write cycle, 8 bits of data, MSB first, are latched on
eight rising SCK edges into an 8-bit data holder.
If CD=0, the data byte will be decoded as
command. If CD=1, this 8-bit will be treated as data
and transferred to proper address in the Display
Data RAM on the rising edge of the last SCK pulse.
Pin CD is examined when SCK is pulled low for the
LSB (D0) of each token.
CS1/0
SDA
SCK
CD
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
Figure 5.a:
4-wire Serial Interface (S8)
3-
WIER
S
ERIAL
I
NTERFACE
(S9)
Only write operations are supported in 3-wire serial
mode. Pin CS[1:0] are used for chip select and bus
cycle reset. On each write cycle, the first bit is CD,
which determines the content of the following 8 bits
of data, MSB first. These 8 command or data bits
are latched on rising SCK edges into an 8-bit data
holder. If CD=0, the data byte will be decoded as
command. If CD=1, this 8-bit will be treated as data
and transferred to proper address in the Display
Data RAM at the rising edge of the last SCK pulse.
By sending CD information explicitly in the bit
stream, control pin CD is not used, and should be
connected to either V
DD
or V
SS
.
The toggle of CS0 (or CS1) for each byte of
data/command is recommended but optional.
CS0
SDA
SCK
CD
D7
D6
D5
D4
D3
D2
D1
D0
CD
D7
D6
Figure 5.b:
3-wire Serial Interface (S9)
Version 1.32
21
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