PLL701-50
Low EMI Spread Spectrum Multiplier IC
FEATURES
•
•
•
•
•
•
•
•
Spread Spectrum Clock Generator/Multiplier with
output selectable from 1x to 8x.
13MHz to 224MHz output with output enable.
13MHz to 30 MHz input frequency from crystal or
external clock signal.
Reduced EMI from Spread Spectrum Modulation,
with selectable modulation magnitude for Center
Spread, Down Spread or Asymmetric Spread.
TTL/CMOS compatible outputs.
3.3V Operating Voltage.
150 ps maximum cycle-to-cycle jitter.
Available in 16-Pin 150mil SSOP.
BLOCK DIAGRAM
REF
XIN/FIN
XOUT
SC(0:3)
SD(0:1)
M(0:2)
XTAL
OSC
PLL
SST
Control
Logic
OE
FOUT
DIE PAD CONFIGURATION
69 mil
AVDD
GND
GND
XIN
1700, 2540
18
AVDD
DESCRIPTION
The PLL701-50 is a low EMI Clock Generator and
Multiplier for high-speed digital systems. It uses
PhaseLink’s unique (Patent Pending) Spread
Spectrum Technology (SST) and permits different
levels of EMI reduction by selecting the amplitude of
the applied SST. The SST feature can be disabled.
The chip operates with input frequencies ranging from
13 to 30 MHz and provides 1x to 8x multiplication at
its output.
XOUT/SD0*^
23
22
21
(Optional)
20
(Optional)
19
GNDOSC
25
C501A
A2727
-27
17
16
15
14
13
12
AVDD
REF/SD1*^
VDD
VDD (optional)
VDD (optional)
SC3^
M2^
104 mil
M1^
M0^
28
29
30
10
OE^
OUTPUT CLOCK (FOUT) SELECTION
M2
M1
M0
FIN/XIN
(MHz)
Multiplier
FOUT
(MHz)
TESTB
SC0^
SC1^
33
34
35
1
4 5
6
8
7
FOUT
GNDBUF
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
13
13
14
13
20
17
15
13
~
~
~
~
~
~
~
~
28
28
30
28
30
30
30
28
X1
X2
X3
X4
X5
X6
X7
X8
13 ~ 28
26 ~ 56
42 ~ 90
52 ~ 112
100 ~ 150
102 ~ 180
105 ~ 210
104 ~ 224
SC2^
GND
GND
GND
Y
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
104 x 69 mil
GND
80 micron x 80 micron
10 mil
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 1
PLL701-50
Low EMI Spread Spectrum Multiplier IC
SPREAD SPECTRUM SELECTION TABLE
SD1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
SD0
1
1
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
SC3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SC2
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SC1
0
0
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SC0
0
1
0
0
0
1
1
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Modulation Modulation
Magnitude Frequency
0.250%
0.500%
0.750%
1.250%
1.500%
1.750%
2.000%
C
C
C
C
A
C
A
C
A
C
A
D
C
A
A
C
A
A
C
A
A
C
D
A
A
C
A
A
A
C
A
A
A
C
A
A
A
Modulation Type
± 0.125%
± 0.25%
± 0.375%
± 0.625%
+0.125 ~ -1.125%
± 0.75%
+0.25 ~ -1.25%
± 0.875%
+0.375 ~ -1.375%
± 1.00%
+0.50 ~ -1.5%
-2.00%
± 1.125%
+0.625 ~ -1.625%
+0.125 ~ -2.125%
± 1.25%
+0.25 ~ -2.25%
+0.75 ~ -1.75%
± 1.375%
+0.875 ~ -1.875%
+0.375 ~ -2.375%
± 1.50%
-3.00%
+1.00 ~ -2.00%
+0.50 ~ -2.50%
± 1.625%
+1.125 ~ -2.125%
+0.625 ~ -2.625%
+0.125 ~ -3.125%
± 1.75%
+1.25 ~ -2.25%
+0.75 ~ -2.75%
+0.25 ~ -3.25%
± 1.875%
+1.37 ~ -2.375%
+0.875 ~ -2.875%
+0.375 ~ -3.375%
SST turned off
SST turned off
SST turned off
SST turned off
2.250%
2.500%
2.750%
Fin / 512
3.000%
3.250%
3.500%
3.750%
0.00 %
Notes:
C: Center Spread. A: Asymmetric Spread. D: Down Spread.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 2
PLL701-50
Low EMI Spread Spectrum Multiplier IC
FUNCTIONAL DESCRIPTION
Selectable spread spectrum and modulation magnitude
The PLL701-50 provides selectable multiplier factors (1x to 8X), selectable spread spectrum modulation type, as
well as selectable modulation magnitude. Selection is made by connecting specific input pins to a logical “zero” or
“one”. Pins 6 (SC0), 7 (SC1), 8 (SC2) and 12 (SC3) are used as inputs to select the spread spectrum modulation
magnitude as shown on the spread spectrum selection table (page 2). Pins 3 (M2), 4 (M1), 5 (M0) are used as
inputs to select the multiplication factor as shown on the output clock selection table (page 1). Pin 11 is the output
enable pin, which tri-states all outputs when low (logical “zero”).
In order to reduce the number of pins on the chip, the PLL701-50 uses pins 2 and 14 (XOUT/SD0 and REF/SD1) as
bi-directional pins. The pins serve as modulation type selector inputs (SD0 and SD1) upon power-up (see spread
spectrum selection table on page 2), and as XOUT crystal connection (pin 2), and REF output signal (pin 14) as
soon as the inputs have been latched.
Connecting a selection pin to a logical “one”
All selection pins have an internal pull-up resistor (30kΩ for pins 3, 4, 5, 6, 7, 8, 11, 12, 14 and 120kΩ for pin 2).
This internal pull-up resistor will pull the input value to a logical “one” (pull-up) by default, i.e. when no resistive
load is connected between the pin and GND. No external pull-up resistor is therefore required for connecting a
logical “one” upon power-up.
Connecting a selection pin to a logical “zero”
For an input only pin, i.e. all input pins except XOUT/SD0 (pin 2) and REF/SD1 (pin 14), the pin simply needs to be
grounded to pull the input down to a logical “zero”. For the Bidirectional pins ( pins 2 and 14 ) you will need an
external resistor. For pin 2 a 27kΩ resistor is recommended and for pin 14 a 4.7kΩ resistor is recommended.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 3
PLL701-50
Low EMI Spread Spectrum Multiplier IC
2. DC/AC Specifications
PARAMETERS
Supply Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
Input Frequency
Maximum interruption of F
IN
Load Capacitance
Pull-up Resistor
Pull-up Resistor
Short Circuit Current
3.3V Dynamic Supply Current
C
L
R
up
R
up
I
sc
I
CC
SYMBOL
V
DD
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
F
XIN
F
IN
CONDITIONS
MIN.
2.97
0.7* V
DD
TYP.
MAX.
3.63
0.3* V
DD
100
100
UNITS
V
V
V
µA
µA
I
OH
=5mA, V
DD
=3.3V
I
OL
=6mA, V
DD
=3.3V
When using a crystal
When using reference clock
When using reference clock
Between Pin XIN and
XOUT*
PIN 2
PIN 3,4,5,6,7,8,11,12,14
No Load
2.4
0.4
See Output Clock Selection table
on page 1
See Output Clock Selection table
on page 1
100
18
120
30
50
20
MHz
MHz
µs
pF
kΩ
kΩ
mA
mA
*Note:
Pin XIN and XOUT each has a 36pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 18pF. If driving XIN
with a reference clock signal, the load capacitance will be 36pF (typical).
3. Timing Characteristics
PARAMETERS
Rise Time
Fall Time
Output Duty Cycle
Cycle to Cycle Jitter
Cycle to Cycle Jitter
SYMBOL
T
r
T
f
D
T
T
cyc-cyc
T
cyc-cyc
CONDITIONS
Measured at 0.8V ~ 2.0V @ 3.3V
Measured at 2.0V ~ 0.8V @ 3.3V
X1, X2, X4, X8 FOUT @ 3.3V
X3, X5, X6, X7 FOUT @ 3.3V
MIN.
0.8
0.78
45
TYP.
0.95
0.85
50
MAX.
1.1
0.9
55
100
150
UNITS
ns
ns
%
ps
ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 4
PLL701-50
Low EMI Spread Spectrum Multiplier IC
PAD ASSIGNMENT
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Name
SC2
N/C
N/C
GND
GND
GND
GNDBUF
FOUT
N/C
OE
N/C
SC3
VDD (Optional)
VDD (Optional)
VDD
REF/SD1
AVDD
AVDD
AVDD
GND (Optional)
GND (Optional)
XIN
XOUT/SD0
N/C
GNDOSC
N/C
N/C
M2
M1
M0
N/C
N/C
TESTB
SC0
SC1
(LOWER LEFT CORNER: X = 0, Y = 0)
X (µm)
Y (µm)
338.9
569
780.5
1027.6
1127.3
1284.5
1595.1
1595.1
1595.1
1595.1
1595.1
1595.1
1595.1
1595.1
1595.1
1595.1
1595.1
1595.1
1369.2
1037.3
824.7
529.7
105.6
105.6
105.6
105.6
105.6
105.6
105.6
105.6
105.6
105.6
105.6
105.6
105.6
104.7
104.7
104.7
104.7
104.7
104.7
139.7
381.7
596.3
811.9
970.3
1069.3
1312.3
1555.6
1656.8
1879.9
2093
2390.6
2435
2435
2435
2435
2343.5
2136.1
2035.6
1934.9
1741.5
1641.4
1396.2
1180.3
993.5
836.7
680.1
354.9
110.7
Disables multiplication and SST when pulled low. For crystal fine tuning.
Internal pull up.
Digital control input to select SS modulation magnitude.30kΩ internal pull-up.
Digital control input to select SS modulation magnitude.30kΩ internal pull-up.
Digital control input to select multiplier. 30kΩ internal pull-up.
Digital control input to select multiplier. 30kΩ internal pull-up.
Digital control input to select multiplier. 30kΩ internal pull-up.
Ground, Oscillator Circuitry
Digital control input to select SS modulation magnitude.30kΩ internal pull-up.
3.3V power supply, Optional
3.3V power supply, Optional
3.3V power supply.
At power-up, this pin acts as input pin to select the modulation type and is
latched in. After the input sampling, this pin provides a buffered Reference
Clock Output of the same frequency as the crystal or clock input. 30kΩ
internal pull-up.
3.3V Analog power supply.
3.3V Analog power supply.
3.3V Analog power supply.
Ground, Optional
Ground, Optional
Crystal input to be connected to fundamental parallel mode crystal. (C
L
=18pF)
or clock input.
At power-up, this pin is acts as input pin to select the modulation type. After
the input sampling, it is used as crystal output connector. 120kΩ internal pull
up resistor.
Output Enable. When low, Tri-states all outputs. 30kΩ internal pull-up.
Ground.
Ground.
Ground.
Ground, Buffer Circuitry
Modulated Clock Frequency Output. The input frequency is multiplied per
M(0:2), modulation type is selected per SD(0:1) and modulation rate is
selected per SC(0:3).
Description
Digital control input to select SS modulation magnitude.30kΩ internal pull-up.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 5
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